--- a/venus/src/core/dbb_block.v	Fri Nov 19 05:58:21 2021 +0000
+++ b/venus/src/core/dbb_block.v	Fri Nov 19 06:09:13 2021 +0000
@@ -3,7 +3,7 @@
  *
  * - star points and bypass capacitors for the powering arrangement;
  * - the 32 kHz xtal circuit with its special ground;
- * - nIBOOT, IDDQ, SIM_CD and SIM_PWCTRL tie-offs;
+ * - nIBOOT, IDDQ and SIM_PWCTRL tie-offs;
  * - nBSCAN and nEMU[1:0] no-connects.
  *
  * All other Calypso signals are passed through untouched.
@@ -24,7 +24,7 @@
 		  BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
 		  VDX, VDR, VFSRX, VCLKRX,
 		  MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
-		  SIM_IO, SIM_CLK, SIM_RST);
+		  SIM_IO, SIM_CLK, SIM_RST, SIM_CD);
 
 input GND, Vdbb, Vio, Vflash, Vrtc;
 
@@ -78,6 +78,7 @@
 
 inout SIM_IO;
 output SIM_CLK, SIM_RST;
+input SIM_CD;
 
 /* nets inside this module */
 wire SIM_PWCTRL;
@@ -179,7 +180,7 @@
 			.SIM_IO(SIM_IO),
 			.SIM_CLK(SIM_CLK),
 			.SIM_RST(SIM_RST),
-			.SIM_CD(Vio),
+			.SIM_CD(SIM_CD),
 			.SIM_PWCTRL_IO5(SIM_PWCTRL));
 
 /* power bypass caps, absolutely unchanged from Leonardo */