FreeCalypso > hg > freecalypso-schem2
diff venus/src/core/rf_pa_block.v @ 9:3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Fri, 19 Nov 2021 05:58:21 +0000 |
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| children |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/venus/src/core/rf_pa_block.v Fri Nov 19 05:58:21 2021 +0000 @@ -0,0 +1,46 @@ +/* + * This module encapsulates the RF PA along with its power bypass caps + * and the Rs and Cs on the control inputs. + */ + +module rf_pa_block (GND, VBAT, Band_Select, Tx_Enable, APC_in, + LB_RF_in, HB_RF_in, LB_RF_out, HB_RF_out); + +input GND, VBAT; +input Band_Select, Tx_Enable, APC_in; +input LB_RF_in, HB_RF_in; +output LB_RF_out, HB_RF_out; + +/* + * A little bit of muck with the control inputs, following Leonardo + * and Openmoko schematics. On FC Venus we completely eliminate + * R621 and R622. + */ + +wire APC_after_resistor; + +resistor R623 (APC_in, APC_after_resistor); +capacitor C648 (APC_after_resistor, GND); +capacitor C656 (Band_Select, GND); + +/* instantiate the PA itself */ + +RF3166 PA (.HB_RF_in(HB_RF_in), + .Band_Select(Band_Select), + .Tx_Enable(Tx_Enable), + .Vbatt(VBAT), + .GND(GND), + .Vramp(APC_after_resistor), + .LB_RF_in(LB_RF_in), + .LB_RF_out(LB_RF_out), + .HB_RF_out(HB_RF_out) + ); + +/* 4 bypass caps per both Leonardo and Openmoko schematics */ + +capacitor C651 (VBAT, GND); +capacitor C652 (VBAT, GND); +capacitor C653 (VBAT, GND); +capacitor C654 (VBAT, GND); + +endmodule
