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comparison venus/src/core/memory.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
parents
children 96e02b1b2374
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8:d23dae52cd7b 9:3ed0f7a9c489
1 module memory (GND, Vflash, Vsram,
2 MCU_A, MCU_D, MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE,
3 Flash_RST, CS_flash1, CS_RAM);
4
5 input GND, Vflash, Vsram;
6 input [22:1] MCU_A;
7 inout [15:0] MCU_D;
8 input MCU_nRD, MCU_nWR, MCU_nBHE, MCU_nBLE;
9 input Flash_RST;
10 input CS_flash1, CS_RAM;
11
12 S71PL064J chip (.Flash_Vcc(Vflash),
13 .RAM_Vcc(Vsram),
14 .Vss(GND),
15 .A(MCU_A),
16 .DQ(MCU_D),
17 .OE(MCU_nRD),
18 .WE(MCU_nWR),
19 .Flash_CE1(CS_flash1),
20 .Flash_RST(Flash_RST),
21 .Flash_WP_ACC(Vflash),
22 .Flash_ready_busy(), /* no connect */
23 .RAM_CE_actlow(CS_RAM),
24 .RAM_CE_acthigh(Vsram),
25 .RAM_UB(MCU_nBHE),
26 .RAM_LB(MCU_nBLE)
27 );
28
29 /* bypass caps */
30 capacitor C318 (Vsram, GND);
31 capacitor C322 (Vflash, GND);
32
33 endmodule