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comparison venus/src/core/calypso_179ghh.v @ 9:3ed0f7a9c489

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Venus: first version of Verilog for the Calypso core
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 19 Nov 2021 05:58:21 +0000
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8:d23dae52cd7b 9:3ed0f7a9c489
1 module calypso_179ghh (TSPCLKX, TSPDO, TSPDI_IO4, TSPEN, TSPACT,
2 DATA, ADD, RnW, nFWE, nFOE, FDP, nBLE, nBHE, nCS,
3 VDDS_MIF, VDDS_1, VDDS_2, VDD, VSS,
4 VDDS_RTC, VDD_RTC, VSS_RTC,
5 VDD_ANG, VSS_ANG, VDD_PLL, VSS_PLL,
6 SCLK, SDO, SDI_SDA, nSCS0_SCL, nSCS1,
7 TX_IRDA, RX_IRDA, TXIR_IRDA, RXIR_IRDA, SD_IRDA,
8 TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, DSR_LPG,
9 MCSI_TXD, MCSI_RXD, MCSI_CLK, MCSI_FSYNCH,
10 KBC, KBR, BU_PWT, LT_PWL, GPIO,
11 nRESET_OUT_IO7, nIBOOT, IDDQ,
12 CLKTCXO, VSSO, OSC32K_IN, OSC32K_OUT,
13 CLK32K_OUT, CLK13M_OUT, nRESPWON, EXT_FIQ, EXT_IRQ,
14 TCXOEN, RFEN, ON_OFF, IT_WAKEUP,
15 nEMU, nBSCAN, TDI, TDO, TCK, TMS,
16 BFSR, BDR, BFSX, BDX, BCLKX_IO6, BCLKR_ARMCLK,
17 VDX, VDR, VFSRX, VCLKRX,
18 MCUDI, MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13,
19 SIM_IO, SIM_CLK, SIM_RST, SIM_CD, SIM_PWCTRL_IO5);
20
21 output TSPCLKX, TSPDO;
22 inout TSPDI_IO4;
23 output [3:0] TSPEN;
24 output [11:0] TSPACT;
25
26 inout [15:0] DATA;
27 output [22:0] ADD;
28 output RnW, nFWE, nFOE, FDP, nBLE, nBHE;
29 output [4:0] nCS;
30
31 input VDDS_MIF, VDDS_1, VDDS_2, VDD, VSS;
32 input VDDS_RTC, VDD_RTC, VSS_RTC;
33 input VDD_ANG, VSS_ANG, VDD_PLL, VSS_PLL;
34
35 output SCLK, SDO, nSCS1;
36 inout SDI_SDA, nSCS0_SCL;
37
38 output TX_IRDA, TXIR_IRDA, SD_IRDA, TX_MODEM, RTS_MODEM;
39 input RX_IRDA, RXIR_IRDA, RX_MODEM, CTS_MODEM;
40 inout DSR_LPG;
41
42 output MCSI_TXD;
43 input MCSI_RXD;
44 inout MCSI_CLK, MCSI_FSYNCH;
45
46 output [4:0] KBC;
47 input [4:0] KBR;
48 output BU_PWT, LT_PWL;
49 inout [3:0] GPIO;
50
51 output nRESET_OUT_IO7;
52 input nIBOOT, IDDQ, CLKTCXO, VSSO;
53 inout OSC32K_IN, OSC32K_OUT;
54 output CLK32K_OUT, CLK13M_OUT;
55 input nRESPWON, EXT_FIQ, EXT_IRQ;
56
57 output TCXOEN, RFEN, IT_WAKEUP;
58 input ON_OFF;
59
60 inout [1:0] nEMU;
61 input nBSCAN, TDI, TCK, TMS;
62 output TDO;
63
64 input BFSR, BDR;
65 output BFSX, BDX;
66 inout BCLKX_IO6;
67 input BCLKR_ARMCLK;
68
69 output VDX;
70 input VDR, VFSRX, VCLKRX;
71
72 input MCUDI;
73 output MCUDO, MCUEN0, MCUEN1_IO8, MCUEN2_IO13;
74
75 inout SIM_IO, SIM_PWCTRL_IO5;
76 output SIM_CLK, SIM_RST;
77 input SIM_CD;
78
79 /* instantiate the package; the mapping of signals to balls is defined here */
80
81 pkg_179GHH pkg (.F3(ADD[0]),
82 .F2(ADD[1]),
83 .G5(ADD[2]),
84 .G4(ADD[3]),
85 .G2(ADD[4]),
86 .G3(ADD[5]),
87 .H1(ADD[6]),
88 .H3(ADD[7]),
89 .H2(ADD[8]),
90 .H4(ADD[9]),
91 .H5(ADD[10]),
92 .J1(ADD[11]),
93 .J2(ADD[12]),
94 .J3(ADD[13]),
95 .J4(ADD[14]),
96 .K3(ADD[15]),
97 .K2(ADD[16]),
98 .K4(ADD[17]),
99 .J5(ADD[18]),
100 .L1(ADD[19]),
101 .L2(ADD[20]),
102 .L3(ADD[21]),
103 .D2(ADD[22]),
104 .B7(DATA[0]),
105 .D7(DATA[1]),
106 .E7(DATA[2]),
107 .D6(DATA[3]),
108 .A6(DATA[4]),
109 .C6(DATA[5]),
110 .E6(DATA[6]),
111 .C5(DATA[7]),
112 .B5(DATA[8]),
113 .D5(DATA[9]),
114 .E5(DATA[10]),
115 .B4(DATA[11]),
116 .C4(DATA[12]),
117 .D4(DATA[13]),
118 .A3(DATA[14]),
119 .B3(DATA[15]),
120 .F4(FDP),
121 .B2(RnW),
122 .F5(nBHE),
123 .E4(nBLE),
124 .C2(nCS[0]),
125 .C3(nCS[1]),
126 .C1(nCS[2]),
127 .D3(nCS[3]),
128 .C11(nCS[4]),
129 .E2(nFOE),
130 .E3(nFWE),
131 .J14(TSPCLKX),
132 .H10(TSPDI_IO4),
133 .H11(TSPDO),
134 .H13(TSPEN[0]),
135 .H12(TSPEN[1]),
136 .H14(TSPEN[2]),
137 .G12(TSPEN[3]),
138 .M12(TSPACT[0]),
139 .M14(TSPACT[1]),
140 .L12(TSPACT[2]),
141 .L13(TSPACT[3]),
142 .J10(TSPACT[4]),
143 .K11(TSPACT[5]),
144 .K13(TSPACT[6]),
145 .K12(TSPACT[7]),
146 .K14(TSPACT[8]),
147 .J11(TSPACT[9]),
148 .J12(TSPACT[10]),
149 .J13(TSPACT[11]),
150 .P9(SCLK),
151 .M9(SDI_SDA),
152 .K8(SDO),
153 .L9(nSCS0_SCL),
154 .N9(nSCS1),
155 .C8(TX_IRDA),
156 .D8(RX_IRDA),
157 .C7(TXIR_IRDA),
158 .A8(RXIR_IRDA),
159 .B8(SD_IRDA),
160 .B9(TX_MODEM),
161 .A9(RX_MODEM),
162 .E8(RTS_MODEM),
163 .D9(DSR_LPG),
164 .C9(CTS_MODEM),
165 .L10(MCSI_TXD),
166 .M10(MCSI_RXD),
167 .N10(MCSI_CLK),
168 .K9(MCSI_FSYNCH),
169 .N4(KBC[0]),
170 .K5(KBC[1]),
171 .L5(KBC[2]),
172 .P5(KBC[3]),
173 .M5(KBC[4]),
174 .K6(KBR[0]),
175 .M6(KBR[1]),
176 .P6(KBR[2]),
177 .N6(KBR[3]),
178 .L6(KBR[4]),
179 .K7(BU_PWT),
180 .L7(LT_PWL),
181 .N3(GPIO[0]),
182 .P3(GPIO[1]),
183 .L4(GPIO[2]),
184 .M4(GPIO[3]),
185 .N2(nRESET_OUT_IO7),
186 .N1(nIBOOT),
187 .M2(IDDQ),
188 .E13(CLKTCXO),
189 .C13(OSC32K_IN),
190 .B13(OSC32K_OUT),
191 .C12(CLK32K_OUT),
192 .F12(CLK13M_OUT),
193 .D12(nRESPWON),
194 .P1(EXT_FIQ),
195 .M3(EXT_IRQ),
196 .A4(VDDS_MIF),
197 .B6(VDDS_MIF),
198 .G1(VDDS_MIF),
199 .D1(VDDS_MIF),
200 .A11(VDDS_2),
201 .L14(VDDS_1),
202 .N5(VDDS_1),
203 .A5(VDD),
204 .B12(VDD),
205 .N14(VDD),
206 .P7(VDD),
207 .M1(VDD),
208 .E1(VDD),
209 .F1(VSS),
210 .N8(VSS),
211 .K1(VSS),
212 .P2(VSS),
213 .P4(VSS),
214 .P10(VSS),
215 .P13(VSS),
216 .G14(VSS),
217 .A10(VSS),
218 .A7(VSS),
219 .A2(VSS),
220 .B1(VSS),
221 .D13(VDDS_RTC),
222 .D14(VDD_RTC),
223 .C14(VSS_RTC),
224 .E11(VDD_ANG),
225 .E12(VSS_ANG),
226 .F11(VDD_PLL),
227 .E14(VSS_PLL),
228 .A14(VSSO),
229 .A12(TCXOEN),
230 .A13(RFEN),
231 .F10(ON_OFF),
232 .B14(IT_WAKEUP),
233 .D11(nBSCAN),
234 .B11(nEMU[0]),
235 .E10(nEMU[1]),
236 .D10(TDI),
237 .C10(TDO),
238 .B10(TCK),
239 .E9(TMS),
240 .L11(BFSR),
241 .K10(BDR),
242 .P12(BFSX),
243 .M11(BDX),
244 .P11(BCLKR_ARMCLK),
245 .N11(BCLKX_IO6),
246 .P14(VDX),
247 .N13(VDR),
248 .M13(VFSRX),
249 .N12(VCLKRX),
250 .N7(MCUDI),
251 .M7(MCUDO),
252 .M8(MCUEN0),
253 .P8(MCUEN1_IO8),
254 .L8(MCUEN2_IO13),
255 .G13(SIM_IO),
256 .F13(SIM_CLK),
257 .G10(SIM_RST),
258 .G11(SIM_CD),
259 .F14(SIM_PWCTRL_IO5)
260 );
261
262 endmodule