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comparison venus/src/periph/audio_hso.v @ 58:229f0b2dd1bf

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HSO audio channel implemented
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Dec 2021 03:26:15 +0000
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57:3afd172b83e1 58:229f0b2dd1bf
1 /*
2 * This Verilog module encapsulates our secondary headset audio channel,
3 * connected to Iota headset interface.
4 */
5
6 module audio_hso (GND, Vio, HSMICBIAS, HSMICP, HSO, Detect);
7
8 input GND, Vio;
9 input HSO, HSMICBIAS;
10 output HSMICP, Detect;
11
12 /* internal wires */
13
14 wire EAR_jack, MIC_jack;
15
16 /* instantiate the jack */
17
18 trrs_jack jack (.T(GND),
19 .R(MIC_jack),
20 .R2(EAR_jack),
21 .S(GND),
22 .T_sw(Detect),
23 .R_sw() /* not used */
24 );
25
26 /* output path */
27
28 capacitor HSO_cap (HSO, EAR_jack);
29
30 /* microphone input circuit */
31
32 capacitor C37 (HSMICBIAS, GND);
33 resistor R19 (HSMICBIAS, MIC_jack);
34
35 capacitor C38 (MIC_jack, GND);
36
37 capacitor C23 (MIC_jack, HSMICP);
38 capacitor C22 (HSMICP, GND);
39
40 /* Detect pull-up resistor */
41
42 resistor Detect_pullup (Detect, Vio);
43
44 endmodule