FreeCalypso > hg > freecalypso-schem2

annotate venus/src/core/rfmatch_rita2pa_hb.v @ 93:0a26e46b2fc2

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change VSP tap header to 6 pins, add CLK13M
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 11 Dec 2021 05:38:21 +0000
parents 3ed0f7a9c489
children
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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1 /* RF Tx path from Rita to PA, high bands */
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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2
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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3 module rfmatch_rita2pa_hb (In, Out, GND, VREG3);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
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4
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 input In;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 output Out;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 input GND, VREG3;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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9 wire mid;
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 inductor L600 (In, VREG3);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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12 capacitor C600 (In, mid);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 chip_attenuator R601 (mid, Out, GND, GND);
3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3ed0f7a9c489 Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
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15 endmodule