FreeCalypso > hg > freecalypso-schem2
annotate venus/src/core/rfmatch_rita2pa_hb.v @ 52:06e95ff0023b
ON_nOFF indicator LED implemented
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 27 Nov 2021 18:34:05 +0000 |
| parents | 3ed0f7a9c489 |
| children |
| rev | line source |
|---|---|
|
9
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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1 /* RF Tx path from Rita to PA, high bands */ |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 module rfmatch_rita2pa_hb (In, Out, GND, VREG3); |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 |
|
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 input In; |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 output Out; |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 input GND, VREG3; |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 |
|
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 wire mid; |
|
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 |
|
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 inductor L600 (In, VREG3); |
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3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 capacitor C600 (In, mid); |
|
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 chip_attenuator R601 (mid, Out, GND, GND); |
|
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 |
|
3ed0f7a9c489
Venus: first version of Verilog for the Calypso core
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 endmodule |
