FreeCalypso > hg > freecalypso-reveng

comparison bootrom.notes @ 20:a52e76c12e6b

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boot ROM re: some sensible documentation written up
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Thu, 25 Apr 2013 06:56:17 +0000
parents 123cb5021b64
children cf3b4cb3d212
comparison
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19:2d9c927cc24b 20:a52e76c12e6b
51 Seems to be a reset command that throws everything back to the initial state. 51 Seems to be a reset command that throws everything back to the initial state.
52 Does not seem to produce a response. 52 Does not seem to produce a response.
53 53
54 <b 54 <b
55 55
56 Followed by 4 bytes, giving a 32-bit value in MSB-first order. The value is 56 Branch command.
57 written to 80052C, and the 0x2c8 function returns code 6. 57
58 Followed by 4 bytes, giving the 32-bit branch address in MSB-first order.
59 It is a BX-style address, i.e., setting the least significant bit will
60 cause the code to be jumped to in the Thumb state.
61
62 The address is written to 80052C, and the 0x2c8 function returns code 6.
63
64 If the command is accepted, a '>b' response is sent back before the
65 jump is performed. If the command is rejected because the downloader
66 is in the wrong state (see below), a '>B' response is sent back, and
67 the downloader is reset to its initial state, waiting for commands at
68 19200 baud.
58 69
59 <c 70 <c
60 71
61 Checksum verification command. The <c characters need to be followed by a 72 Checksum verification command. The <c characters need to be followed by a
62 single binary byte, which need to equal the one's complement of the low byte 73 single binary byte, which need to equal the one's complement of the low byte
67 <i 78 <i
68 79
69 Calls the 0x11c routine, then responds with '>i'. 80 Calls the 0x11c routine, then responds with '>i'.
70 81
71 <p 82 <p
83
84 Set parameters
72 85
73 Followed by 9 bytes: 86 Followed by 9 bytes:
74 1 byte: goes into var at 800518, selects the baud rate: 87 1 byte: goes into var at 800518, selects the baud rate:
75 0: 115200 88 0: 115200
76 1: 57600 89 1: 57600
98 111
99 Error response: >P 112 Error response: >P
100 113
101 <w 114 <w
102 115
116 Write data to RAM
117
103 Followed by: 118 Followed by:
104 1 byte: block number (of this block) 119 1 byte: block number (of this block)
105 1 byte: total # of blocks 120 1 byte: total # of blocks
106 2 bytes: # of payload bytes in this block (MSB first) 121 2 bytes: # of payload bytes in this block (MSB first)
107 4 bytes: load address for this block (MSB first) 122 4 bytes: load address for this block (MSB first)
125 of the above sum, and adds that (plain ripple-carry addition) 140 of the above sum, and adds that (plain ripple-carry addition)
126 to the accum in 800528 (a 16-bit variable). 141 to the accum in 800528 (a 16-bit variable).
127 142
128 Good response: >w 143 Good response: >w
129 Error response: >W <err code byte from 800531> 144 Error response: >W <err code byte from 800531>
145
146 UART download procedure
147
148 Step 1: the external host sends a continuous stream of '<i' beacons at 19200
149 baud, waiting for a '>i' response at the same baud rate. These beacons need
150 to be pouring down the wire into the Calypso UART while waiting for the user
151 to induce the Calypso target into executing the boot ROM (via battery
152 manipulations or other target-specific tricks).
153
154 Step 2: when a '>i' response has been received, send a '<p' command with the
155 desired parameters. Expect a '>p' 00 04 response, still at the original
156 baud rate of 19200; if this response isn't received, it's an error.
157
158 Step 2a: if the '<p' command specified a switch to a higher baud rate (up to
159 115200), have the external host switch its serial port configuration at this
160 point, after getting the >p response but before sending the next command.
161
162 Step 3: send a series of '<w' commands, loading code into IRAM. (Only the
163 internal Calypso RAM may be loaded, not board level RAM.) Maintain a
164 running checksum like the boot ROM does.
165
166 Step 4: send a '<c' command with the proper checksum value. A positive
167 response must be received before one can proceed to the branch.
168
169 Step 5: send a '<b' command to transfer control to the just-loaded code.
170
171 The implementation of this protocol on the boot ROM side contains a state
172 machine which enforces the above order:
173
174 * a '<p' command is required before '<w' will be accepted
175 * after that '<p', one or more '<w's and a '<c' with the correct checksum
176 value must be received in order to enable the '<b' command.
177
178 Errors result in the state machine being reset to the initial state;
179 the baud rate at which the boot ROM expects to receive commands reverts
180 to the initial 19200.
130 181
131 RAM layout: 182 RAM layout:
132 183
133 800000 7 words: 184 800000 7 words:
134 soft-vector pointers: by default the following 7 words at 185 soft-vector pointers: by default the following 7 words at