FreeCalypso > hg > freecalypso-reveng
comparison se_k200i/reg-read @ 397:421273705a75
se_k200i/reg-read: new data capture
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 01 Jan 2023 02:48:46 +0000 |
| parents | |
| children |
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| 396:4e2cb88d8427 | 397:421273705a75 |
|---|---|
| 1 Register reads made with fc-tmsh against original fw: | |
| 2 | |
| 3 MEMIF block: | |
| 4 | |
| 5 FFFF:FB00 = 0x00A4 (nCS0) | |
| 6 FFFF:FB02 = 0x00A5 (nCS1) | |
| 7 FFFF:FB04 = 0x00A4 (nCS2) | |
| 8 FFFF:FB06 = 0x00A5 (nCS3) | |
| 9 FFFF:FB08 = 0x0040 (nCS7) | |
| 10 FFFF:FB0A = 0x0285 (nCS4) | |
| 11 FFFF:FB0C = 0x00C0 (nCS6) | |
| 12 FFFF:FB0E = 0x002A (API-RHEA ctrl) | |
| 13 FFFF:FB10 = 0x0300 (Extra ctrl, boot mapping) | |
| 14 | |
| 15 Config regs: | |
| 16 | |
| 17 FFFE:F004 = 0x0000 (DSP_CONF_REG) | |
| 18 FFFE:F006 = 0x0008 (ARM_CONF_REG: ADD22 set) | |
| 19 FFFE:F008 = 0x3050 (ASIC_CONF_REG) | |
| 20 FFFE:F00A = 0x03FD (IO_CONF_REG: all GPIO except SIM_PWCTRL) | |
| 21 | |
| 22 DPLL & clock ctrl: | |
| 23 | |
| 24 FFFF:9800 = 0x2413 (DPLL multiplies by 8) | |
| 25 FFFF:FD00 = 0xF0A1 (ARM clock is /2) | |
| 26 FFFF:FD02 = 0xFF85 (VTCXO_DIV2 set) | |
| 27 FFFF:FD04 = 0xFFFD (DSP out of reset) | |
| 28 | |
| 29 ARMIO block: | |
| 30 | |
| 31 FFFE:4802 = 0x1F87 (ARMIO_LATCH_OUT) | |
| 32 FFFE:4804 = 0xC060 (IO_CNTL_REG) | |
| 33 | |
| 34 Iota registers: | |
| 35 | |
| 36 APCOFF = 0x07F |