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MEMIF-wait-states: updates for the newly discovered CAL000/A v0.8 document
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 10 Nov 2019 01:26:11 +0000
parents 3d65bdaf00da
children
comparison
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24:00216b7cfc4d 25:c01155dec65b
4 requires some non-trivial analysis. 4 requires some non-trivial analysis.
5 5
6 Calypso MEMIF timings are described on pages 7 through 11 of this TI document: 6 Calypso MEMIF timings are described on pages 7 through 11 of this TI document:
7 7
8 ftp://ftp.freecalypso.org/pub/GSM/Calypso/cal000_a.pdf 8 ftp://ftp.freecalypso.org/pub/GSM/Calypso/cal000_a.pdf
9
10 as well as this more recently discovered newer version:
11
12 ftp://ftp.freecalypso.org/pub/GSM/Calypso/cal000_a_v0.8.pdf
9 13
10 When running on a Calypso C035 target, our TCS211 reference fw as well as most 14 When running on a Calypso C035 target, our TCS211 reference fw as well as most
11 vendor firmwares we've examined run the ARM7 core at its maximum clock frequency 15 vendor firmwares we've examined run the ARM7 core at its maximum clock frequency
12 of 52 MHz. These same firmwares typically configure WS=3 for both flash and 16 of 52 MHz. These same firmwares typically configure WS=3 for both flash and
13 XRAM. Most Calypso-based phones and modems have flash and RAM chips with 70 ns 17 XRAM. Most Calypso-based phones and modems have flash and RAM chips with 70 ns
15 52 MHz and WS=3 was OK for 70 ns memories: one ARM7 clock cycle at 52 MHz is 19 52 MHz and WS=3 was OK for 70 ns memories: one ARM7 clock cycle at 52 MHz is
16 19.23 ns, WS=3 means 4 cycles total per access (it's an N+1 arrangement), 20 19.23 ns, WS=3 means 4 cycles total per access (it's an N+1 arrangement),
17 19.23 ns * 4 = 76.92 ns, thus it should be OK for 70 ns memories, right? Not 21 19.23 ns * 4 = 76.92 ns, thus it should be OK for 70 ns memories, right? Not
18 so fast: as shown in the formula on cal000_a.pdf page 11 and can be seen from 22 so fast: as shown in the formula on cal000_a.pdf page 11 and can be seen from
19 the timing diagrams, two other timing parameters (tda and tsu) also need to be 23 the timing diagrams, two other timing parameters (tda and tsu) also need to be
20 factored in. The sum of tda+tsu for 2.8V MEMIF as given in the only document 24 factored in. The sum of tda+tsu for 2.8V MEMIF as given in the CAL000/A v0.2
21 we have available is 10.5 ns, thus if we run the ARM7 core at 52 MHz and set 25 document is 10.5 ns, thus if we run the ARM7 core at 52 MHz and set WS=3, the
22 WS=3, the available safe window for memory access time is only about 66 ns, 26 available safe window for memory access time is only about 66 ns, which is 4 ns
23 which is 4 ns short of the 70 ns flash and RAM access time specs. 27 short of the 70 ns flash and RAM access time specs.
28
29 The more recently discovered version 0.8 of this same CAL000/A document
30 indicates that the tables for 2.8V and 1.8V MEMIF were erroneously swapped in
31 the older version, and the new correct tda+tsu number for 2.8V MEMIF now appears
32 to be 8.0 ns rather than 10.5 ns. The available safe window for memory access
33 time with WS=3 thus becomes 68.92 ns - this new figure is much closer to 70 ns,
34 but it is still a negative margin, short by 1.08 ns.
24 35
25 TI's reference fw setting of WS=3 in conjuction with ARM7 running at 52 MHz has 36 TI's reference fw setting of WS=3 in conjuction with ARM7 running at 52 MHz has
26 made its way into the official firmwares of Openmoko devices and several Compal 37 made its way into the official firmwares of Openmoko devices and several Compal
27 phones, including Mot C11x/12x, Mot C139/140 and Sony Ericsson J100. At least 38 phones, including Mot C11x/12x, Mot C139/140 and Sony Ericsson J100. At least
28 in the case of Openmoko we know that the hardware features a flash chip with 39 in the case of Openmoko we know that the hardware features a flash chip with
29 70 ns access time (the combined flash+RAM chip is K5A3281CTM-D755, with the 40 70 ns access time (the combined flash+RAM chip is K5A3281CTM-D755, with the
30 suffix meaning 70 ns access time for flash and 55 ns for RAM), and in the case 41 suffix meaning 70 ns access time for flash and 55 ns for RAM), and in the case
31 of Compal phones it is highly unlikely that they used flash chips faster than 42 of Compal phones it is highly unlikely that they used flash chips faster than
32 70 ns, thus we have strong evidence that the access time spec is being violated 43 70 ns, thus we have strong evidence that the access time spec is being violated
33 by about 4 ns. It works in practice because the official specs are guaranteed 44 by about 1.1 ns. It works in practice because the official specs are guaranteed
34 worst-case numbers, but it is still wrong in the strict sense. 45 worst-case numbers and the shortcoming is very small, but it is still wrong in
46 the strict sense.
35 47
36 We have strong evidence that this WS=3 setting comes from TI's mainline 48 We have strong evidence that this WS=3 setting comes from TI's mainline
37 reference fw, as opposed to being customized by or for Openmoko or Compal. 49 reference fw, as opposed to being customized by or for Openmoko or Compal.
38 The evidence is in the following instruction sequence which appears verbatim- 50 The evidence is in the following instruction sequence which appears verbatim-
39 identical across Openmoko's, Mot C11x/12x and C139/140 firmware versions: 51 identical across Openmoko's, Mot C11x/12x and C139/140 firmware versions:
88 on them, and that chip version has no nCS4, only CS4 which is muxed with ADD22 100 on them, and that chip version has no nCS4, only CS4 which is muxed with ADD22
89 and used for the latter on the D-Sample. 101 and used for the latter on the D-Sample.
90 102
91 I further hypothetize that the above MEMIF settings were likely cast into code 103 I further hypothetize that the above MEMIF settings were likely cast into code
92 in the days of Calypso C05, and that the WS=3 setting was computed when the 104 in the days of Calypso C05, and that the WS=3 setting was computed when the
93 ARM7 core ran at 39 MHz. The combination of ARM7 at 39 MHz, WS=3 and the same 105 ARM7 core ran at 39 MHz. The combination of ARM7 at 39 MHz, WS=3 and the more
94 tda+tsu = 10.5 ns adjustment from the available cal000_a.pdf document 106 generous tda+tsu = 10.5 ns adjustment from the older cal000_a.pdf document
95 (officially corresponding to Calypso C035 F751774) gives an access time of 107 (officially corresponding to Calypso C035 F751774) gives an access time of
96 92 ns, which is very sensible. The hypothesis further goes that later TI moved 108 92 ns, which is very sensible. The hypothesis further goes that later TI moved
97 to Calypso C035 silicon and started running the ARM7 core at 52 MHz, but the WS 109 to Calypso C035 silicon and started running the ARM7 core at 52 MHz, but the WS
98 setting was never changed (overlooked), and the 92 ns access time turned into a 110 setting was never changed (overlooked), and the 92 ns access time turned into a
99 mere 66 ns. The latter works with 70 ns memories in practice despite being 111 mere 68.92 ns. The latter works with 70 ns memories in practice despite being
100 strictly incorrect (negative margin), and so the error escaped notice. 112 strictly incorrect (negative margin), and so the error escaped notice.
101 113
102 Solution adopted for FreeCalypso 114 Solution adopted for FreeCalypso
103 ================================ 115 ================================
104 116