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comparison L1/include/l1_defty.h @ 3:f93dab57b032

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L1/include: TCS211-based version restored
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:45:00 +0000
parents 75a11d740a02
children
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2:7c13c26f1aa4 3:f93dab57b032
1 /************* Revision Controle System Header ************* 1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software 2 * GSM Layer 1 software
3 * L1_DEFTY.H 3 * L1_DEFTY.H
4 * 4 *
5 * Filename l1_defty.h 5 * Filename l1_defty.h
6 * Copyright 2003 (C) Texas Instruments 6 * Copyright 2003 (C) Texas Instruments
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9
10 #if (L1_RF_KBD_FIX == 1)
11 #include "l1_macro.h"
12
13 #if(OP_L1_STANDALONE == 0)
14 #include "kpd/kpd_scan_functions.h"
15 #endif
16
17 #endif
18
19 #include "../../gpf/inc/cust_os.h"
20 #if(L1_DYN_DSP_DWNLD == 1) 9 #if(L1_DYN_DSP_DWNLD == 1)
21 #include "../dyn_dwl_include/l1_dyn_dwl_defty.h" 10 #include "../dyn_dwl_include/l1_dyn_dwl_defty.h"
22 #endif 11 #endif
23 #if (L1_AAC == 1) //ADDED for AAC -sajal
24 #include "l1aac_defty.h"
25 #endif
26
27 typedef struct
28 {
29 UWORD8 enable; // activation of FACCH test
30 UWORD8 period; // period of FACCH test
31 }
32 T_FACCH_TEST_PARAMS;
33 12
34 typedef struct 13 typedef struct
35 { 14 {
36 UWORD16 modulus; 15 UWORD16 modulus;
37 UWORD16 relative_position; 16 UWORD16 relative_position;
42 { 21 {
43 UWORD8 schedule_array_size; 22 UWORD8 schedule_array_size;
44 T_BCCHS_SCHEDULE schedule_array[10]; 23 T_BCCHS_SCHEDULE schedule_array[10];
45 } 24 }
46 T_BCCHS; 25 T_BCCHS;
47
48 typedef struct
49 {
50 UWORD8 srr; /* SACCH Repetition Request - UL */
51 UWORD8 sro; /* SACCH Repetition Order - DL */
52 UWORD8 buffer[22+1]; /* New uplink buffer to save the repetition block data in case of retransmission */
53 BOOL buffer_empty; /* It is equal to 1 if the UL repetion buffer should be empty otherwise 0 */
54 }
55 T_REPEAT_SACCH;
56
57 typedef struct
58 {
59 API buffer[12]; /* New buffer to save the DL data for comparison */
60 UWORD8 buffer_empty; /* To indicate the saved buffer */
61 }T_REPEAT_FACCH_PIPELINE;
62 typedef struct
63 {
64 T_REPEAT_FACCH_PIPELINE pipeline[2];
65 UWORD8 counter;
66 UWORD8 counter_candidate;
67 } T_REPEAT_FACCH;
68 26
69 typedef struct 27 typedef struct
70 { 28 {
71 BOOL status; 29 BOOL status;
72 UWORD16 radio_freq; 30 UWORD16 radio_freq;
80 UWORD8 gprs_priority; 38 UWORD8 gprs_priority;
81 UWORD8 sb26_offset; // Set to 1 when SB26 RX win is entirely in frame 25. 39 UWORD8 sb26_offset; // Set to 1 when SB26 RX win is entirely in frame 25.
82 #if (L1_12NEIGH ==1) 40 #if (L1_12NEIGH ==1)
83 UWORD32 fn_offset_mem; 41 UWORD32 fn_offset_mem;
84 UWORD32 time_alignmt_mem; 42 UWORD32 time_alignmt_mem;
85 #endif // (L1_12NEIGH ==1)
86 #if ((REL99 == 1) && ((FF_BHO == 1) || (FF_RTD == 1)))
87 UWORD8 nb_fb_attempt ;
88 UWORD8 fb26_position; // used for RTD feature
89 #endif 43 #endif
90 } 44 }
91 T_NCELL_SINGLE; 45 T_NCELL_SINGLE;
92
93 #if ((REL99 == 1) && (FF_BHO == 1))
94 typedef struct
95 {
96 UWORD8 fb_found_attempt;
97 UWORD16 radio_freq;
98 UWORD32 fn_offset;
99 UWORD32 time_alignmt;
100 UWORD32 fb_toa;
101 }
102 T_BHO_PARAM;
103 #endif // #if ((REL99 == 1) && (FF_BHO == 1))
104 46
105 typedef struct 47 typedef struct
106 { 48 {
107 UWORD8 active_neigh_id_norm; 49 UWORD8 active_neigh_id_norm;
108 UWORD8 active_neigh_tc_norm; 50 UWORD8 active_neigh_tc_norm;
185 T_AMR_CONFIGURATION; 127 T_AMR_CONFIGURATION;
186 #endif 128 #endif
187 129
188 typedef struct 130 typedef struct
189 { 131 {
190 #if(L1_A5_3 == 1 && OP_L1_STANDALONE != 1)
191 UWORD8 A[15+1];
192 #else
193 UWORD8 A[7+1]; 132 UWORD8 A[7+1];
194 #endif
195 } 133 }
196 T_ENCRYPTION_KEY; 134 T_ENCRYPTION_KEY;
197 135
198 typedef struct 136 typedef struct
199 { 137 {
325 } 263 }
326 T_HO_PARAMS; 264 T_HO_PARAMS;
327 265
328 typedef struct 266 typedef struct
329 { 267 {
268 T_CHANNEL_DESCRIPTION channel_desc;
269 T_MOBILE_ALLOCATION frequency_list;
270 T_STARTING_TIME starting_time;
271 }
272 T_MPHC_CHANGE_FREQUENCY;
273
274 typedef struct
275 {
330 UWORD8 subchannel; 276 UWORD8 subchannel;
331 UWORD8 channel_mode; 277 UWORD8 channel_mode;
332 #if (AMR == 1) 278 #if (AMR == 1)
333 T_AMR_CONFIGURATION amr_configuration; 279 T_AMR_CONFIGURATION amr_configuration;
334 #endif 280 #endif
335 } 281 }
336 T_MPHC_CHANNEL_MODE_MODIFY_REQ; 282 T_MPHC_CHANNEL_MODE_MODIFY_REQ;
337 283
338 typedef struct 284 typedef struct
339 { 285 {
286 UWORD8 cipher_mode;
287 UWORD8 a5_algorithm;
288 T_ENCRYPTION_KEY new_ciph_param;
289 }
290 T_MPHC_SET_CIPHERING_REQ;
291
292 typedef struct
293 {
340 UWORD8 sub_channel; 294 UWORD8 sub_channel;
341 UWORD8 frame_erasure; 295 UWORD8 frame_erasure;
342 } 296 }
343 T_OML1_CLOSE_TCH_LOOP_REQ; 297 T_OML1_CLOSE_TCH_LOOP_REQ;
344 298
396 { 350 {
397 const T_FCT *address; 351 const T_FCT *address;
398 UWORD8 size; 352 UWORD8 size;
399 } 353 }
400 T_TASK_MFTAB; 354 T_TASK_MFTAB;
401
402
403 #if (GSM_IDLE_RAM != 0)
404 typedef struct
405 {
406 BOOL l1s_full_exec;
407 BOOL trff_ctrl_enable_cause_int;
408 WORD32 hw_timer;
409 WORD32 os_load;
410 UWORD32 sleep_mode;
411
412 #if GSM_IDLE_RAM_DEBUG
413 UWORD32 killing_flash_access;
414 UWORD32 killing_ext_ram_access;
415 UWORD32 irq;
416 UWORD32 fiq;
417 UWORD32 nb_inth;
418
419 #if (CHIPSET == 10) && (OP_WCP == 1)
420 UWORD16 TC_true_control;
421 #endif // CHIPSET && OP_WCP
422 #endif // GSM_IDLE_RAM_DEBUG
423 UWORD32 task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR];
424 UWORD32 mem_task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR];
425 }
426 T_L1S_GSM_IDLE_INTRAM;
427 #endif // GSM_IDLE_RAM
428
429 355
430 /***********************************************************/ 356 /***********************************************************/
431 /* TPU controle register components definition. */ 357 /* TPU controle register components definition. */
432 /***********************************************************/ 358 /***********************************************************/
433 359
466 /* */ 392 /* */
467 /***********************************************************/ 393 /***********************************************************/
468 394
469 typedef struct 395 typedef struct
470 { 396 {
471 API d_task_d; // 0x0800 (0) Downlink task command. 397 API d_task_d; // (0) Downlink task command.
472 API d_burst_d; // 0x0801 (1) Downlink burst identifier. 398 API d_burst_d; // (1) Downlink burst identifier.
473 API d_task_u; // 0x0802 (2) Uplink task command. 399 API d_task_u; // (2) Uplink task command.
474 API d_burst_u; // 0x0803 (3) Uplink burst identifier. 400 API d_burst_u; // (3) Uplink burst identifier.
475 API d_task_md; // 0x0804 (4) Downlink Monitoring (FB/SB) command. 401 API d_task_md; // (4) Downlink Monitoring (FB/SB) command.
476 #if (DSP >= 33) 402 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
477 API d_background; // 0x0805 (5) Background tasks 403 API d_background; // (5) Background tasks
478 #else 404 #else
479 API d_reserved; // 0x0805 (5) Reserved 405 API d_reserved; // (5) Reserved
480 #endif 406 #endif
481 API d_debug; // 0x0806 (6) Debug/Acknowledge/general purpose word. 407 API d_debug; // (6) Debug/Acknowledge/general purpose word.
482 API d_task_ra; // 0x0807 (7) RA task command. 408 API d_task_ra; // (7) RA task command.
483 API d_fn; // 0x0808 (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only. 409 API d_fn; // (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only.
484 // bit [0..7] -> b_fn_report, FN in the normalized reporting period. 410 // bit [0..7] -> b_fn_report, FN in the normalized reporting period.
485 // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning. 411 // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning.
486 API d_ctrl_tch; // 0x0809 (9) Tch channel description. 412 API d_ctrl_tch; // (9) Tch channel description.
487 // bit [0..3] -> b_chan_mode, channel mode. 413 // bit [0..3] -> b_chan_mode, channel mode.
488 // bit [4..5] -> b_chan_type, channel type. 414 // bit [4..5] -> b_chan_type, channel type.
489 // bit [6] -> reset SACCH 415 // bit [6] -> reset SACCH
490 // bit [7] -> vocoder O 416 // bit [7] -> vocoder ON
491 // bit [8] -> b_sync_tch_ul, synchro. TCH/UL. 417 // bit [8] -> b_sync_tch_ul, synchro. TCH/UL.
492 // bit [9] -> b_sync_tch_dl, synchro. TCH/DL. 418 // bit [9] -> b_sync_tch_dl, synchro. TCH/DL.
493 // bit [10] -> b_stop_tch_ul, stop TCH/UL. 419 // bit [10] -> b_stop_tch_ul, stop TCH/UL.
494 // bit [11] -> b_stop_tch_dl, stop TCH/DL. 420 // bit [11] -> b_stop_tch_dl, stop TCH/DL.
495 // bit [12.13] -> b_tch_loop, tch loops A/B/C. 421 // bit [12.13] -> b_tch_loop, tch loops A/B/C.
496 API hole; // 0x080A (10) unused hole. 422 API hole; // (10) unused hole.
497 423
498 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) 424 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
499 API d_ctrl_abb; // 0x080B (11) Bit field indicating the analog baseband register to send. 425 API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send.
500 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB 426 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB
501 // bit [1.2] -> unused 427 // bit [1.2] -> unused
502 // bit [3] -> b_apcdel: delays-register in NDB 428 // bit [3] -> b_apcdel: delays-register in NDB
503 // bit [4] -> b_afc: freq control register in DB 429 // bit [4] -> b_afc: freq control register in DB
504 // bit [5..15] -> unused 430 // bit [5..15] -> unused
505 #endif 431 #endif
506 API a_a5fn[2]; // 0x080C (12..13) Encryption Frame number. 432 API a_a5fn[2]; // (12..13) Encryption Frame number.
507 // word 0, bit [0..4] -> T2. 433 // word 0, bit [0..4] -> T2.
508 // word 0, bit [5..10] -> T3. 434 // word 0, bit [5..10] -> T3.
509 // word 1, bit [0..11] -> T1. 435 // word 1, bit [0..11] -> T1.
510 API d_power_ctl; // 0x080E (14) Power level control. 436 API d_power_ctl; // (14) Power level control.
511 API d_afc; // 0x080F (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb"). 437 API d_afc; // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb").
512 API d_ctrl_system; // 0x0810 (16) Controle Register for RESET/RESUME. 438 API d_ctrl_system; // (16) Controle Register for RESET/RESUME.
513 // bit [0..2] -> b_tsq, training sequence. 439 // bit [0..2] -> b_tsq, training sequence.
514 // bit [3] -> b_bcch_freq_ind, BCCH frequency indication. 440 // bit [3] -> b_bcch_freq_ind, BCCH frequency indication.
515 // bit [15] -> b_task_abort, DSP task abort command. 441 // bit [15] -> b_task_abort, DSP task abort command.
516 // bit [4] -> B_SWH_APPLY_WHITENING, Apply whitening.
517 //#if (((DSP == 36)||(DSP == 37)||(DSP == 38) || (DSP == 39)))
518 // API d_swh_ApplyWhitening_db; // 0x0811 SWH Whitening Activation Flag
519 //#endif
520 } 442 }
521 T_DB_MCU_TO_DSP; 443 T_DB_MCU_TO_DSP;
522 444
523 #if (DSP == 38) || (DSP == 39) 445 typedef struct
524 // DB COMMON to GSM and GPRS 446 {
525 typedef struct 447 API d_task_d; // (0) Downlink task command.
526 { 448 API d_burst_d; // (1) Downlink burst identifier.
527 API d_dco_algo_ctrl_nb; // DRP DCO enable/disable for normal burst 449 API d_task_u; // (2) Uplink task command.
528 API d_dco_algo_ctrl_sb; // DRP DCO enable/disable for synchro burst 450 API d_burst_u; // (3) Uplink burst identifier.
529 API d_dco_algo_ctrl_pw; // DRP DCO enable/disable for power burst 451 API d_task_md; // (4) Downlink Monitoring (FB/SB) task command.
530 API d_swh_ctrl_db; 452 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
531 API d_fast_paging_ctrl; 453 API d_background; // (5) Background tasks
532 }
533 T_DB_COMMON_MCU_TO_DSP;
534 #endif // DSP == 38 || DSP == 39
535
536 /* DSP CPU load measurement */
537 #if (DSP == 38) || (DSP == 39)
538 // DB COMMON to GSM and GPRS
539 typedef struct
540 {
541 API d_dsp_fgd_tsk_tim0;
542 API d_dsp_fgd_tsk_tim1;
543 API d_tdma_dsp_fn;
544 API d_dsp_page_read;
545 }
546 T_DB_MCU_TO_DSP_CPU_LOAD;
547 #endif // DSP == 38 || DSP == 39
548
549 typedef struct
550 {
551 API d_task_d; // 0x0828 (0) Downlink task command.
552 API d_burst_d; // 0x0829 (1) Downlink burst identifier.
553 API d_task_u; // 0x082A (2) Uplink task command.
554 API d_burst_u; // 0x082B (3) Uplink burst identifier.
555 API d_task_md; // 0x082C (4) Downlink Monitoring (FB/SB) task command.
556 #if (DSP >= 33)
557 API d_background; // 0x082D (5) Background tasks
558 #else 454 #else
559 API d_reserved; // 0x082D (5) Reserved 455 API d_reserved; // (5) Reserved
560 #endif 456 #endif
561 API d_debug; // 0x082E (6) Debug/Acknowledge/general purpose word. 457 API d_debug; // (6) Debug/Acknowledge/general purpose word.
562 API d_task_ra; // 0x082F (7) RA task command. 458 API d_task_ra; // (7) RA task command.
563 459
564 #if (DSP >= 33) 460 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
565 API a_serv_demod[4]; // 0x0830 ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). 461 API a_serv_demod[4]; // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
566 API a_pm[3]; // 0x0834 (12..14) Power measurement results, array of 3 words. 462 API a_pm[3]; // (12..14) Power measurement results, array of 3 words.
567 API a_sch[5]; // 0x0837 (15..19) Header + SB information, array of 5 words. 463 API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
568 #else 464 #else
569 API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words. 465 API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words.
570 API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). 466 API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
571 API a_sch[5]; // (15..19) Header + SB information, array of 5 words. 467 API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
572 #endif 468 #endif
573 } 469 }
574 T_DB_DSP_TO_MCU; 470 T_DB_DSP_TO_MCU;
575 471
576 #if (DSP == 38) || (DSP == 39) 472 #if (DSP == 34) || (DSP == 35) || (DSP == 36) // NDB GSM
577 typedef struct
578 {
579 // MISC Tasks
580 API d_dsp_page; // 0x08D4
581
582 // DSP status returned (DSP --> MCU).
583 API d_error_status; // 0x08D5
584
585 // RIF control (MCU -> DSP). // following is removed for Locosto
586 API d_spcx_rif_hole; // 0x08D6
587
588
589 API d_tch_mode; // 0x08D7 TCH mode register.
590 // bit [0..1] -> b_dai_mode.
591 // bit [2] -> b_dtx.
592
593 API d_debug1; // 0x08D8 bit 0 at 1 enable dsp f_tx delay for Omega
594
595 API d_dsp_test; // 0x08D9
596
597 // Words dedicated to Software version (DSP code + Patch)
598 API d_version_number1; // 0x08DA
599 API d_version_number2; // 0x08DB
600
601 API d_debug_ptr; // 0x08DC
602 API d_debug_bk; // 0x08DD
603
604 API d_pll_config; // 0x08DE
605
606 // GSM/GPRS DSP Debug trace support
607 API p_debug_buffer; // 0x08DF
608 API d_debug_buffer_size; // 0x08E0
609 API d_debug_trace_type; // 0x08E1
610
611 #if (W_A_DSP_IDLE3 == 1)
612 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
613 API d_dsp_state; // 0x08E2
614 // 5 words are reserved for any possible mapping modification
615 API d_hole1_ndb[2]; // 0x08E3
616 #else
617 // 6 words are reserved for any possible mapping modification
618 API d_hole1_ndb[3];
619 #endif
620
621 #if (AMR == 1)
622 API p_debug_amr; // 0x08E5??? DSP doc says reserved
623 #else
624 API d_hole_debug_amr;
625 #endif
626
627 API d_dsp_iq_scaling_factor; // 0x08E6
628 API d_mcsi_select; // 0x08E7
629
630 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
631 API d_apcdel1_bis; // 0x08E8
632 API d_apcdel2_bis;
633 // New registers due to IOTA analog base band
634 API d_apcdel2;
635
636
637 API d_vbctrl2_hole; // 0x08EB
638 API d_bulgcal_hole; // 0x08EC
639 // Analog Based Band - removed in ROM 38
640 API d_afcctladd_hole; // 0x08ED
641 API d_vbuctrl_hole; // 0x08EE - removed in ROM38
642 API d_vbdctrl_hole; // 0x08EF - removed in ROM38
643
644 API d_apcdel1; // 0x08F0
645 // New Variables Added due to the APC Switch
646 // But for when DSP is in Idle3 all writes from MCU to APC are routed via DSP
647 API d_apclev; // APCLEV - 0x08F1 (In ROM36 - apcoff )
648 // NOTE: Used Only in Test mode
649 // Only when l1_config.tmode.rf_params.down_up == TMODE_UPLINK;
650 API d_apcctrl2; // APCCTRL2 - 0x08F2 (In ROM36 - bulioff)
651 API d_bulqoff_hole; // 0x08F3
652 API d_dai_onoff; // 0x08F4
653 API d_auxdac_hole; // 0x08F5
654
655 API d_vbctrl_hole; // 0x08F6 - removed in ROM38
656
657 API d_bbctrl_hole; // 0x08F7 - removed in ROM38
658
659 // Monitoring tasks control (MCU <- DSP)
660 // FB task
661 API d_fb_det; // 0x08F8 FB detection result. (1 for FOUND).
662 API d_fb_mode; // Mode for FB detection algorithm.
663 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
664
665 // SB Task
666 API a_sch26[5]; // 0x08FE Header + SB information, array of 5 words.
667
668 API d_audio_gain_ul; // 0x0903
669 API d_audio_gain_dl; // 0x0904
670
671 // Controller of the melody E2 audio compressor - removed in ROM 38
672 API d_audio_compressor_ctrl_hole; // 0x0905 - removed in ROM37,38
673
674 // AUDIO module
675 API d_audio_init; // 0x0906
676 API d_audio_status; //
677
678 // Audio tasks
679 // TONES (MCU -> DSP)
680 API d_toneskb_init;
681 API d_toneskb_status;
682 API d_k_x1_t0;
683 API d_k_x1_t1;
684 API d_k_x1_t2;
685 API d_pe_rep;
686 API d_pe_off;
687 API d_se_off;
688 API d_bu_off; // 0x0910
689 API d_t0_on;
690 API d_t0_off;
691 API d_t1_on;
692 API d_t1_off;
693 API d_t2_on;
694 API d_t2_off;
695 API d_k_x1_kt0;
696 API d_k_x1_kt1;
697 API d_dur_kb;
698 API d_shiftdl;
699 API d_shiftul; // 0x091B
700
701 API d_aec_18_hole; // 0x091C
702
703 API d_es_level_api;
704 API d_mu_api;
705
706 // Melody Ringer module
707 API d_melo_osc_used; // 0x091F
708 API d_melo_osc_active; // 0x0920
709 API a_melo_note0[4];
710 API a_melo_note1[4];
711 API a_melo_note2[4];
712 API a_melo_note3[4];
713 API a_melo_note4[4];
714 API a_melo_note5[4];
715 API a_melo_note6[4];
716 API a_melo_note7[4];
717
718 // selection of the melody format
719 API d_melody_selection; // 0x0941
720
721 // Holes due to the format melody E1
722 API a_melo_holes[3];
723
724 // Speech Recognition module - Removed in ROM38
725 API d_sr_holes[19]; // 0x0945
726
727 // Audio buffer
728 API a_dd_1[22]; // 0x0958 Header + DATA traffic downlink information, sub. chan. 1.
729 API a_du_1[22]; // 0x096E Header + DATA traffic uplink information, sub. chan. 1.
730
731 // V42bis module
732 API d_v42b_nego0; // 0x0984
733 API d_v42b_nego1;
734 API d_v42b_control;
735 API d_v42b_ratio_ind;
736 API d_mcu_control;
737 API d_mcu_control_sema;
738
739 // Background tasks
740 API d_background_enable; // 0x098A
741 API d_background_abort;
742 API d_background_state;
743 API d_max_background;
744 API a_background_tasks[16]; // 0x098E
745 API a_back_task_io[16]; //0x099E
746
747 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
748 API d_gea_mode_ovly_hole; // 0x09AE
749 API a_gea_kc_ovly_hole[4]; // 0x09AF
750
751 API d_hole3_ndb[6]; //0x09B3
752 API d_dsp_aud_hint_flag; // 0x09B9;
753
754 // word used for the init of USF threshold
755 API d_thr_usf_detect; // 0x09BA
756
757 // Encryption module
758 API d_a5mode; // Encryption Mode.
759
760 API d_sched_mode_gprs_ovly; // 0x09Bc
761 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1)
762 API d_hole1_fast_ndb[1]; // 0x09BD;
763 API d_dsp_hint_flag; // 0x09BE; //used for fast usf and fast dtx and other dyn dwn
764 // 6 words are reserved for any possible mapping modification
765 #if FF_L1_IT_DSP_DTX
766 API d_fast_dtx_enable;//used for enabling fast dtx- 0x09BF
767 API d_fast_dtx_enc_data;//fast usf written by DSP to indicate tx data is there or not- 0x09C0
768 #else // FF_L1_IT_DSP_DTX
769 API d_hole3_fast_ndb[2]; // 0x09BF
770 #endif // FF_L1_IT_DSP_USF
771 #if (FF_L1_FAST_DECODING == 1)
772 API d_fast_paging_data; // 0x9C1
773 #else
774 API d_hole_fast_paging_ndb;
775 #endif /* FF_L1_FAST_DECODING*/
776 #else
777 // 7 words are reserved for any possible mapping modification
778 API d_hole4_ndb[5]; // 0x09BD
779 #endif
780
781 // Ramp definition for Omega device
782 API a_ramp_hole[16]; //0x09C2
783
784 // CCCH/SACCH downlink information...(!!)
785 API a_cd[15]; //0x09D2 Header + CCCH/SACCH downlink information.
786
787 // FACCH downlink information........(!!)
788 API a_fd[15]; // 0x09E1 Header + FACCH downlink information.
789
790 // Traffic downlink data frames......(!!)
791 API a_dd_0[22]; // 0x09F0 Header + DATA traffic downlink information, sub. chan. 0.
792
793 // CCCH/SACCH uplink information.....(!!)
794 API a_cu[15]; // 0x0A06 Header + CCCH/SACCH uplink information.
795
796 // FACCH downlink information........(!!)
797 API a_fu[15]; // 0x0A15 Header + FACCH uplink information
798
799 // Traffic downlink data frames......(!!)
800 API a_du_0[22]; // 0x0A24 Header + DATA traffic uplink information, sub. chan. 0.
801
802 // Random access.....................(MCU -> DSP).
803 API d_rach; // 0x0A3A RACH information.
804
805 //...................................(MCU -> DSP).
806 API a_kc[4]; // 0x0A3B Encryption Key Code.
807
808 // Integrated Data Services module
809 API d_ra_conf;
810 API d_ra_act;
811 API d_ra_test;
812 API d_ra_statu;
813 API d_ra_statd;
814 API d_fax;
815 API a_data_buf_ul[21]; // 0x0A45
816 API a_data_buf_dl[37]; // 0x0A5A
817
818 API a_sr_holes0[422]; // 0x0A7F
819
820 #if (L1_AEC == 1)
821 #if (L1_NEW_AEC)
822 API d_cont_filter;
823 API d_granularity_att;
824 API d_coef_smooth;
825 API d_es_level_max;
826 API d_fact_vad;
827 API d_thrs_abs;
828 API d_fact_asd_fil;
829 API d_fact_asd_mut;
830 API d_far_end_pow_h;
831 API d_far_end_pow_l;
832 API d_far_end_noise_h;
833 API d_far_end_noise_l;
834 #else
835 API a_sr_hole1[12];
836 #endif
837 #else
838 API a_sr_hole2[12];
839 #endif
840
841 // Speech recognition model
842 API a_sr_holes1[145]; // 0x0C31
843
844 // Correction of PR G23M/L1_MCU-SPR-15494
845 API d_cport_init; // 0x0CC2
846 API d_cport_ctrl;
847 API a_cport_cfr[2];
848 API d_cport_tcl_tadt;
849 API d_cport_tdat;
850 API d_cport_tvs;
851 API d_cport_status;
852 API d_cport_reg_value;
853 API a_cport_holes[1011];
854
855 API a_model_holes[1041];
856
857 // EOTD buffer
858 #if (L1_EOTD==1)
859 API d_eotd_first;
860 API d_eotd_max;
861 API d_eotd_nrj_high;
862 API d_eotd_nrj_low;
863 API a_eotd_crosscor[18];
864 #else
865 API a_eotd_holes[22];
866 #endif
867 // AMR ver 1.0 buffers
868 API a_amr_config[4]; // 0x14E5
869 API a_ratscch_ul[6];
870 API a_ratscch_dl[6];
871 API d_amr_snr_est; // estimation of the SNR of the AMR speech block
872 #if (L1_VOICE_MEMO_AMR)
873 API d_amms_ul_voc;
874 #else
875 API a_voice_memo_amr_holes[1];
876 #endif
877 API d_thr_onset_afs; // thresh detection ONSET AFS
878 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
879 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
880 API d_thr_update_afs; // thresh detection SID_UPDATE AFS
881 API d_thr_onset_ahs; // thresh detection ONSET AHS
882 API d_thr_sid_ahs; // thresh detection SID frames AHS
883 API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER
884 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
885 API d_thr_soft_bits; // 0x14FF
886
887
888 API a_amrschd_debug[30]; // 0x1500
889 #if (W_A_AMR_THRESHOLDS)
890 API a_d_macc_thr_afs[8]; // 0x151E
891 API a_d_macc_thr_ahs[6]; // 0x1526
892 #else
893 API d_holes[14]; // 0x151E
894 #endif
895
896 // There is no melody E2 in DSP ROM38 as of now -> Only Holes
897 API d_melody_e2_holes[17]; // 0x152C
898
899
900 API d_vol_ul_level_hole; // 0x153D
901 API d_vol_dl_level_hole; // 0x153E
902 API d_vol_speed_hole; // 0x153F
903 API d_sidetone_level_hole; // 0x1540
904
905 // Audio control area
906 API d_es_ctrl; // 0x1541
907 API d_anr_ul_ctrl;
908 API d_aec_ul_ctrl;
909 API d_agc_ul_ctrl;
910 //API d_aqi_ctrl_hole1[4]; // Reserved for future UL modules earlier code now modified and added d_vad_noise_ene_ndb
911 API d_aqi_ctrl_hole1[1]; // Reserved for future UL modules
912
913 API d_vad_noise_ene_ndb[2]; //NAVC API address-0x1546-MSB, 0x1547-LSB-> 2-WORDs
914
915 API d_navc_ctrl_status; // NAVC control
916
917 API d_iir_dl_ctrl; // 0x1549
918 API d_lim_dl_ctrl;
919 API d_drc_dl_ctrl;
920 API d_agc_dl_ctrl;
921 API d_audio_apps_ctrl; // Reserved for future DL modules
922 API d_audio_apps_status;
923 API d_aqi_status;
924
925 #if (L1_IIR == 1)
926 API d_iir_input_scaling; // 0x1550
927 API d_iir_fir_scaling; //
928 API d_iir_input_gain_scaling; //
929 API d_iir_output_gain_scaling; //
930 API d_iir_output_gain; //
931 API d_iir_feedback; //
932 API d_iir_nb_iir_blocks; //
933 API d_iir_nb_fir_coefs; //
934 API a_iir_iir_coefs[80]; // 0x1558
935 API a_iir_fir_coefs[32]; // 0x15A8
936
937 #if (L1_ANR == 1)
938 API d_anr_min_gain;
939 API d_anr_vad_thr;
940 API d_anr_gamma_slow;
941 API d_anr_gamma_fast;
942 API d_anr_gamma_gain_slow;
943 API d_anr_gamma_gain_fast;
944 API d_anr_thr2;
945 API d_anr_thr4;
946 API d_anr_thr5;
947 API d_anr_mean_ratio_thr1;
948 API d_anr_mean_ratio_thr2;
949 API d_anr_mean_ratio_thr3;
950 API d_anr_mean_ratio_thr4;
951 API d_anr_div_factor_shift;
952 API d_anr_ns_level;
953 #else
954 API d_anr_hole[15];
955 #endif
956
957
958 #elif (L1_IIR == 2) //Srart address= 0x1550.
959 API d_iir4x_control;
960 API d_iir4x_frame_size;
961 API d_iir4x_fir_swap;
962 API d_iir4x_fir_enable;
963 API d_iir4x_fir_length;
964 API_SIGNED d_iir4x_fir_shift;
965 API_SIGNED a_iir4x_fir_taps[40];
966 API d_iir4x_sos_enable;
967 API d_iir4x_sos_number;
968 API_SIGNED d_iir4x_sos_fact_1;
969 API_SIGNED d_iir4x_sos_fact_form_1;
970 API_SIGNED a_iir4x_sos_den_1[2];
971 API_SIGNED a_iir4x_sos_num_1[3];
972 API_SIGNED d_iir4x_sos_num_form_1;
973 API_SIGNED d_iir4x_sos_fact_2;
974 API_SIGNED d_iir4x_sos_fact_form_2;
975 API_SIGNED a_iir4x_sos_den_2[2];
976 API_SIGNED a_iir4x_sos_num_2[3];
977 API_SIGNED d_iir4x_sos_num_form_2;
978 API_SIGNED d_iir4x_sos_fact_3;
979 API_SIGNED d_iir4x_sos_fact_form_3;
980 API_SIGNED a_iir4x_sos_den_3[2];
981 API_SIGNED a_iir4x_sos_num_3[3];
982 API_SIGNED d_iir4x_sos_num_form_3;
983 API_SIGNED d_iir4x_sos_fact_4;
984 API_SIGNED d_iir4x_sos_fact_form_4;
985 API_SIGNED a_iir4x_sos_den_4[2];
986 API_SIGNED a_iir4x_sos_num_4[3];
987 API_SIGNED d_iir4x_sos_num_form_4;
988 API_SIGNED d_iir4x_sos_fact_5;
989 API_SIGNED d_iir4x_sos_fact_form_5;
990 API_SIGNED a_iir4x_sos_den_5[2];
991 API_SIGNED a_iir4x_sos_num_5[3];
992 API_SIGNED d_iir4x_sos_num_form_5;
993 API_SIGNED d_iir4x_sos_fact_6;
994 API_SIGNED d_iir4x_sos_fact_form_6;
995 API_SIGNED a_iir4x_sos_den_6[2];
996 API_SIGNED a_iir4x_sos_num_6[3];
997 API_SIGNED d_iir4x_sos_num_form_6;
998 API_SIGNED d_iir4x_gain; //End address= 0x15B0
999
1000
1001 #if (L1_AGC_UL == 1) //Start address= 0x15B1
1002 // AGC uplink
1003 API d_agc_ul_control;
1004 API d_agc_ul_frame_size;
1005 API_SIGNED d_agc_ul_targeted_level;
1006 API_SIGNED d_agc_ul_signal_up;
1007 API_SIGNED d_agc_ul_signal_down;
1008 API_SIGNED d_agc_ul_max_scale;
1009 API_SIGNED d_agc_ul_gain_smooth_alpha;
1010 API_SIGNED d_agc_ul_gain_smooth_alpha_fast;
1011 API_SIGNED d_agc_ul_gain_smooth_beta;
1012 API_SIGNED d_agc_ul_gain_smooth_beta_fast;
1013 API_SIGNED d_agc_ul_gain_intp_flag;
1014 #else
1015 API d_agc_ul_holes[11];
1016 #endif //End address= 0x15BB
1017
1018 #if (L1_AGC_DL == 1)
1019 // AGC downlink
1020 API d_agc_dl_control; //Start Address= 0x15BC
1021 API d_agc_dl_frame_size;
1022 API_SIGNED d_agc_dl_targeted_level;
1023 API_SIGNED d_agc_dl_signal_up;
1024 API_SIGNED d_agc_dl_signal_down;
1025 API_SIGNED d_agc_dl_max_scale;
1026 API_SIGNED d_agc_dl_gain_smooth_alpha;
1027 API_SIGNED d_agc_dl_gain_smooth_alpha_fast;
1028 API_SIGNED d_agc_dl_gain_smooth_beta;
1029 API_SIGNED d_agc_dl_gain_smooth_beta_fast;
1030 API_SIGNED d_agc_dl_gain_intp_flag;
1031 #else
1032 API d_agc_dl_holes[11];
1033 #endif //End address= 0x15C6
1034
1035
1036 #if(L1_AEC == 2)
1037 API d_aec_mode; //Start address= 0x15C7
1038 API d_mu;
1039 API d_cont_filter;
1040 API d_scale_input_ul;
1041 API d_scale_input_dl;
1042 API d_div_dmax;
1043 API d_div_swap_good;
1044 API d_div_swap_bad;
1045 API d_block_init;
1046 API d_fact_vad;
1047 API d_fact_asd_fil;
1048 API d_fact_asd_mut;
1049 API d_thrs_abs;
1050 API d_es_level_max;
1051 API d_granularity_att;
1052 API d_coef_smooth; //End address= 0x15D6
1053
1054 #else
1055
1056 #if (L1_ANR == 1)
1057 API d_iir_holes[1];
1058
1059 API d_anr_min_gain;
1060 API d_anr_vad_thr;
1061 API d_anr_gamma_slow;
1062 API d_anr_gamma_fast;
1063 API d_anr_gamma_gain_slow;
1064 API d_anr_gamma_gain_fast;
1065 API d_anr_thr2;
1066 API d_anr_thr4;
1067 API d_anr_thr5;
1068 API d_anr_mean_ratio_thr1;
1069 API d_anr_mean_ratio_thr2;
1070 API d_anr_mean_ratio_thr3;
1071 API d_anr_mean_ratio_thr4;
1072 API d_anr_div_factor_shift;
1073 API d_anr_ns_level;
1074 #else
1075 API d_iir_anr_hole[16];
1076 #endif
1077 #endif
1078
1079
1080 #else
1081 API d_iir_holes_1[97];
1082 #if (L1_AGC_UL == 1)
1083 // AGC uplink
1084 API d_agc_ul_control;
1085 API d_agc_ul_frame_size;
1086 API_SIGNED d_agc_ul_targeted_level;
1087 API_SIGNED d_agc_ul_signal_up;
1088 API_SIGNED d_agc_ul_signal_down;
1089 API_SIGNED d_agc_ul_max_scale;
1090 API_SIGNED d_agc_ul_gain_smooth_alpha;
1091 API_SIGNED d_agc_ul_gain_smooth_alpha_fast;
1092 API_SIGNED d_agc_ul_gain_smooth_beta;
1093 API_SIGNED d_agc_ul_gain_smooth_beta_fast;
1094 API_SIGNED d_agc_ul_gain_intp_flag;
1095 #else
1096 API d_agc_ul_holes[11];
1097 #endif
1098
1099 #if (L1_AGC_DL == 1)
1100 // AGC downlink
1101 API d_agc_dl_control;
1102 API d_agc_dl_frame_size;
1103 API_SIGNED d_agc_dl_targeted_level;
1104 API_SIGNED d_agc_dl_signal_up;
1105 API_SIGNED d_agc_dl_signal_down;
1106 API_SIGNED d_agc_dl_max_scale;
1107 API_SIGNED d_agc_dl_gain_smooth_alpha;
1108 API_SIGNED d_agc_dl_gain_smooth_alpha_fast;
1109 API_SIGNED d_agc_dl_gain_smooth_beta;
1110 API_SIGNED d_agc_dl_gain_smooth_beta_fast;
1111 API_SIGNED d_agc_dl_gain_intp_flag;
1112 #else
1113 API d_agc_dl_holes[11];
1114 #endif
1115
1116 #if(L1_AEC == 2)
1117 API d_aec_mode;
1118 API d_mu;
1119 API d_cont_filter;
1120 API d_scale_input_ul;
1121 API d_scale_input_dl;
1122 API d_div_dmax;
1123 API d_div_swap_good;
1124 API d_div_swap_bad;
1125 API d_block_init;
1126 API d_fact_vad;
1127 API d_fact_asd_fil;
1128 API d_fact_asd_mut;
1129 API d_thrs_abs;
1130 API d_es_level_max;
1131 API d_granularity_att;
1132 API d_coef_smooth;
1133
1134 #else
1135
1136 #if(L1_ANR == 1)
1137 API d_iir_holes[1];
1138
1139 API d_anr_min_gain;
1140 API d_anr_vad_thr;
1141 API d_anr_gamma_slow;
1142 API d_anr_gamma_fast;
1143 API d_anr_gamma_gain_slow;
1144 API d_anr_gamma_gain_fast;
1145 API d_anr_thr2;
1146 API d_anr_thr4;
1147 API d_anr_thr5;
1148 API d_anr_mean_ratio_thr1;
1149 API d_anr_mean_ratio_thr2;
1150 API d_anr_mean_ratio_thr3;
1151 API d_anr_mean_ratio_thr4;
1152 API d_anr_div_factor_shift;
1153 API d_anr_ns_level;
1154 #else
1155 API d_iir_anr_hole[16];
1156 #endif
1157
1158 #endif
1159
1160 #endif //L1_IIR
1161
1162 #if (L1_LIMITER == 1)
1163 API a_lim_mul_low[2]; // 0x15D7
1164 API a_lim_mul_high[2];
1165 API d_lim_gain_fall_q15; // 0x15DB
1166 API d_lim_gain_rise_q15; //
1167 API d_lim_block_size; // 0x15DD
1168 API d_lim_nb_fir_coefs; //
1169 API d_lim_slope_update_period;
1170 API a_lim_filter_coefs[16]; // 0x15E0
1171 #else
1172 API d_lim_hole[25];
1173 #endif
1174 #if (L1_ES == 1)
1175 API d_es_mode; // 0x15F0
1176 API d_es_gain_dl;
1177 API d_es_gain_ul_1;
1178 API d_es_gain_ul_2;
1179 API d_es_tcl_fe_ls_thr;
1180 API d_es_tcl_dt_ls_thr;
1181 API d_es_tcl_fe_ns_thr;
1182 API d_es_tcl_dt_ns_thr;
1183 API d_es_tcl_ne_thr;
1184 API d_es_ref_ls_pwr;
1185 API d_es_switching_time;
1186 API d_es_switching_time_dt;
1187 API d_es_hang_time;
1188 API a_es_gain_lin_dl_vect[4];
1189 API a_es_gain_lin_ul_vect[4];
1190 #else
1191 API d_es_hole[21];
1192 #endif
1193
1194 #if (L1_ANR == 2)
1195 API_SIGNED d_anr_ns_level; // start address= 0x1605
1196 API_SIGNED d_anr_control;
1197 API_SIGNED d_anr_tone_ene_th;
1198 API_SIGNED d_anr_tone_cnt_th;
1199 #else
1200 API d_anr_hole_2[4];
1201 #endif //End address= 0x1608
1202
1203 #if (L1_WCM == 1) // start address= 0x1609
1204 API_SIGNED d_wcm_mode;
1205 API_SIGNED d_wcm_frame_size;
1206 API_SIGNED d_wcm_num_sub_frames;
1207 API_SIGNED d_wcm_ratio;
1208 API_SIGNED d_wcm_threshold;
1209 API_SIGNED a_wcm_gain[16];
1210 #else
1211 API_SIGNED d_wcm_holes[21];
1212 #endif
1213
1214 API a_tty_holes1[24]; // 0x161E
1215
1216 #if (L1_GTT == 1)
1217 API d_tty_status; // 0x1636
1218 API d_ctm_detect_shift; // 0x1637
1219 API d_tty2x_baudot_mod_amplitude_scale;
1220 API d_tty2x_samples_per_baudot_stop_bit;
1221 API d_tty_reset_buffer_ul;
1222 API d_tty_loop_ctrl;
1223 API p_tty_loop_buffer;
1224 API d_ctm_mod_norm;
1225 API d_tty2x_offset_normalization;
1226 API d_tty2x_threshold_startbit;
1227 API d_tty2x_threshold_diff; // 0x1640
1228 API d_tty2x_duration_startdetect; // 0x1641
1229 API d_tty2x_startbit_thres; // 0x1642
1230 API d_tty2x_hole_init_mute_frame_count; // 0x1643
1231 API d_tty2x_dl_bypass_mute; // 0x1644
1232 #else
1233 API a_tty_holes2[15];
1234 #endif
1235
1236 API a_tty_fifo_holes[131]; // 0x1645
1237
1238 // New DRP Releated Variables Start Here
1239 API a_drp_holes_1[6]; // 0x16C8
1240 API d_drp_apcctrl2_hole; // 0x16CE - APC control register 2
1241 API d_drp_afc_add_api; // 0x16CF - Address where AFC value needs to be written
1242 API a_drp_holes_2[12]; // 0x16D0
1243 API a_drp_ramp[20]; // 0x16DC - Power ramp up/down in DRP registers format
1244 API a_drp_holes_3[271]; // 0x16F0
1245
1246
1247 API d_dsp_write_debug_pointer; // 0x17FF
1248
1249 #if (MELODY_E2)
1250 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; // 0x1800
1251 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
1252 API a_dsp_after_trace_holes[7440-(SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE + SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT)];
1253 #else
1254 API a_dsp_trace[C_DEBUG_BUFFER_SIZE]; // 0x1800;
1255 API a_dsp_after_trace_holes[7440-C_DEBUG_BUFFER_SIZE]; // 0x1800 + C_DEBUG_BUFFER_SIZE
1256 // In this region MP3 variables are placed + holes
1257 #endif
1258
1259 #if (L1_PCM_EXTRACTION)
1260 API a_pcm_api_download[160];
1261 API a_pcm_api_upload[160];
1262 API a_pcm_holes1[8];
1263 API d_pcm_api_upload;
1264 API d_pcm_api_download;
1265 API d_pcm_api_error;
1266 API a_pcm_holes2[1181];
1267 #else
1268 API a_pcm_holes[1512];
1269 #endif
1270
1271 #if REL99
1272 #if FF_EMR
1273 API a_mean_cv_bep_page_0[3];//0x3AF8
1274 API a_mean_cv_bep_padding_0;
1275 API a_mean_cv_bep_page_1[3];
1276 API a_mean_cv_bep_padding_1;
1277 API a_emr_holes2[378];
1278 #endif
1279 #else // L1_R99
1280 API a_emr_holes1[386];
1281 #endif // L1_R99
1282
1283 // SAIC related
1284 API a_swh_hole[16]; // 0x3C7A
1285 API d_swh_flag_ndb; // 0x3C8A - SWH (whitening) on / off flag
1286 API d_swh_Clipping_Threshold_ndb; // 0x3C8B - Threshold to which the DSP shall clip the SNR
1287
1288 // A5/3 related
1289 API a_a5_kc[8]; // 0x3C8C
1290
1291 // DCO related
1292 API d_dco_samples_per_symbol; // 0x3C94 No. of samples per symbol (IQ pair)
1293 API d_dco_fcw; // 0x3C95 Control word to tell the IF Frequency
1294 API a_dco_hole[15]; // 0x3C96 Hole related to DCO
1295
1296 // A5/3 related
1297 // API a_a5_holes[801]; // 0x3CA5
1298
1299 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 ))
1300 API a_a5_holes[286]; // 0x3CA5
1301 API d_chase_comb_ctrl; // 0x3DC3 Control for the chase combine feature
1302 API a_a5_holes1[514]; // 0x3DC4
1303 #else
1304 // A5/3 related
1305 API a_a5_holes[801]; // 0x3CA5
1306 #endif /* (FF_REPEATED_SACCH == 1) */
1307
1308
1309
1310 }
1311 T_NDB_MCU_DSP;
1312
1313 #elif (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) // NDB GSM
1314 typedef struct 473 typedef struct
1315 { 474 {
1316 // MISC Tasks 475 // MISC Tasks
1317 API d_dsp_page; 476 API d_dsp_page;
1318 477
1358 API p_debug_amr; 517 API p_debug_amr;
1359 #else 518 #else
1360 API d_hole_debug_amr; 519 API d_hole_debug_amr;
1361 #endif 520 #endif
1362 521
1363 #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 522 #if (CHIPSET == 12)
1364 #if (DSP == 35) || (DSP == 36) || (DSP == 37) 523 #if (DSP == 35) || (DSP == 36)
1365 API d_hole2_ndb[1]; 524 API d_hole2_ndb[1];
1366 API d_mcsi_select; 525 API d_mcsi_select;
1367 #else 526 #else
1368 API d_hole2_ndb[2]; 527 API d_hole2_ndb[2];
1369 #endif 528 #endif
1396 #if (ANALOG == 1) 555 #if (ANALOG == 1)
1397 API d_vbctrl; 556 API d_vbctrl;
1398 #elif ((ANALOG == 2) || (ANALOG == 3)) 557 #elif ((ANALOG == 2) || (ANALOG == 3))
1399 API d_vbctrl1; 558 API d_vbctrl1;
1400 #endif 559 #endif
1401 560
1402 API d_bbctrl; 561 API d_bbctrl;
1403 562
1404 // Monitoring tasks control (MCU <- DSP) 563 // Monitoring tasks control (MCU <- DSP)
1405 // FB task 564 // FB task
1406 API d_fb_det; // FB detection result. (1 for FOUND). 565 API d_fb_det; // FB detection result. (1 for FOUND).
1507 API d_vau_delay_init; 666 API d_vau_delay_init;
1508 API d_vaud_cfg; 667 API d_vaud_cfg;
1509 API d_vauo_onoff; 668 API d_vauo_onoff;
1510 API d_vaus_vol; 669 API d_vaus_vol;
1511 API d_vaud_pll; 670 API d_vaud_pll;
1512 API d_togbr2; 671 API d_hole3_ndb[1];
1513 #elif ((ANALOG == 1) || (ANALOG == 2)) 672 #elif ((ANALOG == 1) || (ANALOG == 2))
673
1514 API d_hole3_ndb[7]; 674 API d_hole3_ndb[7];
675
1515 #endif 676 #endif
1516 677
1517 // word used for the init of USF threshold 678 // word used for the init of USF threshold
1518 API d_thr_usf_detect; 679 API d_thr_usf_detect;
1519 680
1563 API a_data_buf_dl[37]; 724 API a_data_buf_dl[37];
1564 725
1565 // GTT API mapping for DSP code 34 (for test only) 726 // GTT API mapping for DSP code 34 (for test only)
1566 #if (L1_GTT == 1) 727 #if (L1_GTT == 1)
1567 API d_tty_status; 728 API d_tty_status;
729 API d_tty_detect_thres;
1568 API d_ctm_detect_shift; 730 API d_ctm_detect_shift;
1569 API d_tty2x_baudot_mod_amplitude_scale; 731 API d_tty_fa_thres;
1570 API d_tty2x_samples_per_baudot_stop_bit; 732 API d_tty_mod_norm;
1571 API d_tty_reset_buffer_ul; 733 API d_tty_reset_buffer_ul;
1572 API d_tty_loop_ctrl; 734 API d_tty_loop_ctrl;
1573 API p_tty_loop_buffer; 735 API p_tty_loop_buffer;
1574 API d_ctm_mod_norm;
1575 API d_tty2x_offset_normalization;
1576 API d_tty2x_threshold_startbit;
1577 API d_tty2x_threshold_diff;
1578 API d_tty2x_duration_startdetect;
1579 API d_tty2x_startbit_thres;
1580 #else 736 #else
1581 API a_tty_holes[13]; 737 API a_tty_holes[8];
1582 #endif 738 #endif
1583 739
1584 API a_sr_holes0[409]; 740 API a_sr_holes0[414];
1585
1586 741
1587 #if (L1_NEW_AEC) 742 #if (L1_NEW_AEC)
1588 // new AEC 743 // new AEC
1589 API d_cont_filter; 744 API d_cont_filter;
1590 API d_granularity_att; 745 API d_granularity_att;
1602 API a_new_aec_holes[12]; 757 API a_new_aec_holes[12];
1603 #endif // L1_NEW_AEC 758 #endif // L1_NEW_AEC
1604 759
1605 // Speech recognition model 760 // Speech recognition model
1606 API a_sr_holes1[145]; 761 API a_sr_holes1[145];
1607
1608 // Correction of PR G23M/L1_MCU-SPR-15494
1609 #if ((CHIPSET == 12) || (CHIPSET == 4) || (CODE_VERSION == SIMULATION))
1610 API d_cport_init; 762 API d_cport_init;
1611 API d_cport_ctrl; 763 API d_cport_ctrl;
1612 API a_cport_cfr[2]; 764 API a_cport_cfr[2];
1613 API d_cport_tcl_tadt; 765 API d_cport_tcl_tadt;
1614 API d_cport_tdat; 766 API d_cport_tdat;
1615 API d_cport_tvs; 767 API d_cport_tvs;
1616 API d_cport_status; 768 API d_cport_status;
1617 API d_cport_reg_value; 769 API d_cport_reg_value;
1618 770
1619 API a_cport_holes[1011]; 771 API a_cport_holes[1011];
1620 #else // CHIPSET != 12
1621 API a_cport_holes[1020];
1622 #endif // CHIPSET == 12
1623 772
1624 API a_model[1041]; 773 API a_model[1041];
1625 774
1626 // EOTD buffer 775 // EOTD buffer
1627 #if (L1_EOTD==1) 776 #if (L1_EOTD==1)
1641 #if (L1_VOICE_MEMO_AMR) 790 #if (L1_VOICE_MEMO_AMR)
1642 API d_amms_ul_voc; 791 API d_amms_ul_voc;
1643 #else 792 #else
1644 API a_voice_memo_amr_holes[1]; 793 API a_voice_memo_amr_holes[1];
1645 #endif 794 #endif
1646 API d_thr_onset_afs; // thresh detection ONSET AFS 795 API d_thr_onset_afs; // thresh detection ONSET AFS
1647 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS 796 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
1648 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS 797 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
1649 API d_thr_update_afs; // thresh detection SID_UPDATE AFS 798 API d_thr_update_afs; // thresh detection SID_UPDATE AFS
1650 API d_thr_onset_ahs; // thresh detection ONSET AHS 799 API d_thr_onset_ahs; // thresh detection ONSET AHS
1651 API d_thr_sid_ahs; // thresh detection SID frames AHS 800 API d_thr_sid_ahs; // thresh detection SID frames AHS
1652 API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER 801 API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER
1653 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA 802 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
1654 API d_thr_soft_bits; 803 API d_thr_soft_bits;
1655
1656 #if ((CODE_VERSION == SIMULATION) || (DSP != 37))
1657 #if (MELODY_E2) 804 #if (MELODY_E2)
1658 API d_melody_e2_osc_stop; 805 API d_melody_e2_osc_stop;
1659 API d_melody_e2_osc_active; 806 API d_melody_e2_osc_active;
1660 API d_melody_e2_semaphore; 807 API d_melody_e2_semaphore;
1661 API a_melody_e2_osc[16][3]; 808 API a_melody_e2_osc[16][3];
1662 API d_melody_e2_globaltimefactor; 809 API d_melody_e2_globaltimefactor;
1663 API a_melody_e2_instrument_ptr[8]; 810 API a_melody_e2_instrument_ptr[8];
1664 API d_melody_e2_deltatime; 811 API d_melody_e2_deltatime;
1665 #else 812
1666 API d_melody_e2_holes[61]; 813 #if (AMR_THRESHOLDS_WORKAROUND)
1667 #endif 814 API a_d_macc_thr_afs[8];
1668 #else // (DSP == 37) 815 API a_d_macc_thr_ahs[6];
1669 API a_amrschd_debug[30]; // 0x1500
1670 #if (W_A_AMR_THRESHOLDS)
1671 API a_d_macc_thr_afs[8]; // 0x151E
1672 API a_d_macc_thr_ahs[6]; // 0x1526
1673 #else
1674 API a_d_macc_thr_holes[14]; // 0x151E
1675 #endif
1676 API d_melody_e2_holes[17]; //0x152C - This is not a melody E2 hole; But named like that;
1677 #endif
1678
1679 #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)) || (CODE_VERSION == SIMULATION)) // Calypso+ or Perseus2 or Samson
1680 API d_vol_ul_level;
1681 API d_vol_dl_level;
1682 API d_vol_speed;
1683 API d_sidetone_level;
1684
1685 // Audio control area
1686 API d_es_ctrl;
1687 API d_anr_ul_ctrl;
1688
1689 #if ((DSP == 36) || (DSP == 37))
1690
1691 API d_aqi_ctrl_hole1_1[3];
1692 #if (L1_SAIC != 0)
1693 API d_swh_flag_ndb;
1694 API d_swh_Clipping_Threshold_ndb;
1695 #else
1696 API d_swh_hole[2];
1697 #endif
1698 API d_aqi_ctrl_hole1_2[1];
1699 #else 816 #else
1700 API d_aqi_ctrl_hole1[6]; // Reserved for future UL modules 817 API a_melody_e2_holes0[14];
1701 #endif 818 #endif
1702 API d_iir_dl_ctrl; 819
1703 API d_lim_dl_ctrl; 820 API a_melody_e2_holes1[693];
1704 API d_aqi_ctrl_hole2[4]; // Reserved for future DL modules
1705 API d_aqi_status;
1706
1707 #if (L1_IIR == 1)
1708 API d_iir_input_scaling;
1709 API d_iir_fir_scaling;
1710 API d_iir_input_gain_scaling;
1711 API d_iir_output_gain_scaling;
1712 API d_iir_output_gain;
1713 API d_iir_feedback;
1714 API d_iir_nb_iir_blocks;
1715 API d_iir_nb_fir_coefs;
1716 API a_iir_iir_coefs[80];
1717 API a_iir_fir_coefs[32];
1718 #else
1719 API d_iir_hole[120];
1720 #endif
1721
1722 #if (L1_ANR == 1)
1723 API d_anr_min_gain;
1724 API d_anr_vad_thr;
1725 API d_anr_gamma_slow;
1726 API d_anr_gamma_fast;
1727 API d_anr_gamma_gain_slow;
1728 API d_anr_gamma_gain_fast;
1729 API d_anr_thr2;
1730 API d_anr_thr4;
1731 API d_anr_thr5;
1732 API d_anr_mean_ratio_thr1;
1733 API d_anr_mean_ratio_thr2;
1734 API d_anr_mean_ratio_thr3;
1735 API d_anr_mean_ratio_thr4;
1736 API d_anr_div_factor_shift;
1737 API d_anr_ns_level;
1738 #else
1739 API d_anr_hole[15];
1740 #endif
1741
1742 #if (L1_LIMITER == 1)
1743 API a_lim_mul_low[2];
1744 API a_lim_mul_high[2];
1745 API d_lim_gain_fall_q15;
1746 API d_lim_gain_rise_q15;
1747 API d_lim_block_size;
1748 API d_lim_nb_fir_coefs;
1749 API d_lim_slope_update_period;
1750 API a_lim_filter_coefs[16];
1751 #else
1752 API d_lim_hole[25];
1753 #endif
1754 #if (L1_ES == 1)
1755 API d_es_mode;
1756 API d_es_gain_dl;
1757 API d_es_gain_ul_1;
1758 API d_es_gain_ul_2;
1759 API d_es_tcl_fe_ls_thr;
1760 API d_es_tcl_dt_ls_thr;
1761 API d_es_tcl_fe_ns_thr;
1762 API d_es_tcl_dt_ns_thr;
1763 API d_es_tcl_ne_thr;
1764 API d_es_ref_ls_pwr;
1765 API d_es_switching_time;
1766 API d_es_switching_time_dt;
1767 API d_es_hang_time;
1768 API a_es_gain_lin_dl_vect[4];
1769 API a_es_gain_lin_ul_vect[4];
1770 #else
1771 API d_es_hole[21];
1772 #endif
1773
1774 #else // CALYPSO+ or PERSEUS2
1775 API a_calplus_holes[200];
1776 #endif
1777
1778 #if (W_A_AMR_THRESHOLDS)
1779 API d_holes[492];
1780 #if (CODE_VERSION == SIMULATION) || (DSP != 37)
1781 API a_d_macc_thr_afs[8]; // In ROM37 this is moved from 0x17F1 to 0x151E
1782 API a_d_macc_thr_ahs[6];
1783 #else
1784 API d_holes_rom37[14]; // In ROM37 this is moved from 0x17F1 to 0x151E
1785 #endif
1786 API d_one_hole[1];
1787 #else
1788 API d_holes[507];
1789 #endif
1790
1791 #if (MELODY_E2)
1792 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; 821 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
1793 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT]; 822 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
1794 #endif 823 #else
824 API d_holes[61];
825 #if (AMR_THRESHOLDS_WORKAROUND)
826 API a_d_macc_thr_afs[8];
827 API a_d_macc_thr_ahs[6];
828 #endif
829 #endif
830
1795 } 831 }
1796 T_NDB_MCU_DSP; 832 T_NDB_MCU_DSP;
1797 #elif (DSP == 33) // NDB GSM 833 #elif (DSP == 33) // NDB GSM
1798 typedef struct 834 typedef struct
1799 { 835 {
2184 #elif (ANALOG == 2) 1220 #elif (ANALOG == 2)
2185 API d_vbctrl1; 1221 API d_vbctrl1;
2186 #endif 1222 #endif
2187 1223
2188 API d_bbctrl; 1224 API d_bbctrl;
2189 #else 1225 #else
2190 #error DSPCODE not supported with given ANALOG 1226 #error DSPCODE not supported with given ANALOG
2191 #endif //(ANALOG)1, 2 1227 #endif //(ANALOG)1, 2
2192 //...................................(MCU -> DSP). 1228 //...................................(MCU -> DSP).
2193 API a_sch26[5]; // Header + SB information, array of 5 words. 1229 API a_sch26[5]; // Header + SB information, array of 5 words.
2194 1230
2269 API d_audio_status; 1305 API d_audio_status;
2270 1306
2271 #if (L1_EOTD ==1) 1307 #if (L1_EOTD ==1)
2272 API a_eotd_hole[369]; 1308 API a_eotd_hole[369];
2273 1309
2274 API d_eotd_first; 1310 API d_eotd_first;
2275 API d_eotd_max; 1311 API d_eotd_max;
2276 API d_eotd_nrj_high; 1312 API d_eotd_nrj_high;
2277 API d_eotd_nrj_low; 1313 API d_eotd_nrj_low;
2278 API a_eotd_crosscor[18]; 1314 API a_eotd_crosscor[18];
2279 #endif 1315 #endif
2280 #endif 1316 #endif
2281 } 1317 }
2282 T_NDB_MCU_DSP; 1318 T_NDB_MCU_DSP;
2283 1319
2284 1320
2412 #elif (ANALOG == 2) 1448 #elif (ANALOG == 2)
2413 API d_vbctrl1; 1449 API d_vbctrl1;
2414 #endif 1450 #endif
2415 API d_bbctrl; 1451 API d_bbctrl;
2416 1452
2417 #else 1453 #else
2418 #error DSPCODE not supported with given ANALOG 1454 #error DSPCODE not supported with given ANALOG
2419 #endif //(ANALOG)1, 2 1455 #endif //(ANALOG)1, 2
2420 //...................................(MCU -> DSP). 1456 //...................................(MCU -> DSP).
2421 API a_sch26[5]; // Header + SB information, array of 5 words. 1457 API a_sch26[5]; // Header + SB information, array of 5 words.
2422 1458
2423 // TONES.............................(MCU -> DSP) 1459 // TONES.............................(MCU -> DSP)
2501 #endif 1537 #endif
2502 } 1538 }
2503 T_NDB_MCU_DSP; 1539 T_NDB_MCU_DSP;
2504 #endif 1540 #endif
2505 1541
2506 #if (DSP >= 34) 1542 #if (DSP == 34) || (DSP == 35) || (DSP == 36)
2507 typedef struct 1543 typedef struct
2508 { 1544 {
2509 API_SIGNED d_transfer_rate; // 0x0C31 1545 API_SIGNED d_transfer_rate;
2510 1546
2511 // Common GSM/GPRS 1547 // Common GSM/GPRS
2512 // These words specified the latencies to applies on some peripherics 1548 // These words specified the latencies to applies on some peripherics
2513 API_SIGNED d_lat_mcu_bridge; 1549 API_SIGNED d_lat_mcu_bridge;
2514 API_SIGNED d_lat_mcu_hom2sam; 1550 API_SIGNED d_lat_mcu_hom2sam;
2520 1556
2521 API_SIGNED d_misc_config; 1557 API_SIGNED d_misc_config;
2522 1558
2523 API_SIGNED d_cn_sw_workaround; 1559 API_SIGNED d_cn_sw_workaround;
2524 1560
2525 API_SIGNED d_hole2_param[4]; // 0x0C39 1561 API_SIGNED d_hole2_param[4];
2526 1562
2527 //...................................Frequency Burst. 1563 //...................................Frequency Burst.
2528 API_SIGNED d_fb_margin_beg; // 0x0C3D 1564 API_SIGNED d_fb_margin_beg;
2529 API_SIGNED d_fb_margin_end; 1565 API_SIGNED d_fb_margin_end;
2530 API_SIGNED d_nsubb_idle; 1566 API_SIGNED d_nsubb_idle;
2531 API_SIGNED d_nsubb_dedic; 1567 API_SIGNED d_nsubb_dedic;
2532 API_SIGNED d_fb_thr_det_iacq; 1568 API_SIGNED d_fb_thr_det_iacq;
2533 API_SIGNED d_fb_thr_det_track; 1569 API_SIGNED d_fb_thr_det_track;
2552 API_SIGNED d_v42b_switch_min; 1588 API_SIGNED d_v42b_switch_min;
2553 API_SIGNED d_v42b_switch_max; 1589 API_SIGNED d_v42b_switch_max;
2554 API_SIGNED d_v42b_reset_delay; 1590 API_SIGNED d_v42b_reset_delay;
2555 1591
2556 //...................................TCH Half Speech. 1592 //...................................TCH Half Speech.
2557 API_SIGNED d_ldT_hr; // 0x0C53 1593 API_SIGNED d_ldT_hr;
2558 API_SIGNED d_maccthresh_hr; 1594 API_SIGNED d_maccthresh_hr;
2559 API_SIGNED d_maccthresh1_hr; 1595 API_SIGNED d_maccthresh1_hr;
2560 API_SIGNED d_gu_hr; 1596 API_SIGNED d_gu_hr;
2561 API_SIGNED d_go_hr; 1597 API_SIGNED d_go_hr;
2562 API_SIGNED d_b_hr; 1598 API_SIGNED d_b_hr;
2572 API_SIGNED c_b_efr; 1608 API_SIGNED c_b_efr;
2573 API_SIGNED c_sm_efr; 1609 API_SIGNED c_sm_efr;
2574 API_SIGNED c_attmax_efr; 1610 API_SIGNED c_attmax_efr;
2575 1611
2576 //...................................CHED 1612 //...................................CHED
2577 API_SIGNED d_sd_min_thr_tchfs; // 0x0C63 1613 API_SIGNED d_sd_min_thr_tchfs;
2578 API_SIGNED d_ma_min_thr_tchfs; 1614 API_SIGNED d_ma_min_thr_tchfs;
2579 API_SIGNED d_md_max_thr_tchfs; 1615 API_SIGNED d_md_max_thr_tchfs;
2580 API_SIGNED d_md1_max_thr_tchfs; 1616 API_SIGNED d_md1_max_thr_tchfs;
2581 1617
2582 API_SIGNED d_sd_min_thr_tchhs; 1618 API_SIGNED d_sd_min_thr_tchhs;
2599 API_SIGNED d_y_max; 1635 API_SIGNED d_y_max;
2600 API_SIGNED d_wed_diff_threshold; 1636 API_SIGNED d_wed_diff_threshold;
2601 API_SIGNED d_mabfi_min_thr_tchhs; 1637 API_SIGNED d_mabfi_min_thr_tchhs;
2602 1638
2603 // FACCH module 1639 // FACCH module
2604 API_SIGNED d_facch_thr; // 0x0C79 1640 API_SIGNED d_facch_thr;
2605 1641
2606 // IDS module 1642 // IDS module
2607 API_SIGNED d_max_ovsp_ul; // 1643 API_SIGNED d_max_ovsp_ul;
2608 API_SIGNED d_sync_thres; 1644 API_SIGNED d_sync_thres;
2609 API_SIGNED d_idle_thres; 1645 API_SIGNED d_idle_thres;
2610 API_SIGNED d_m1_thres; 1646 API_SIGNED d_m1_thres;
2611 API_SIGNED d_max_ovsp_dl; 1647 API_SIGNED d_max_ovsp_dl;
2612 API_SIGNED d_gsm_bgd_mgt; 1648 API_SIGNED d_gsm_bgd_mgt;
2613 1649
2614 // FIR coefficients 1650 // FIR coefficients
2615 API a_fir_holes[4]; 1651 API a_fir_holes[4];
2616 API a_fir31_uplink[31]; // 0x0C84 1652 API a_fir31_uplink[31];
2617 API a_fir31_downlink[31]; 1653 API a_fir31_downlink[31];
2618 } 1654 }
2619 T_PARAM_MCU_DSP; 1655 T_PARAM_MCU_DSP;
2620 #elif (DSP == 33) 1656 #elif (DSP == 33)
2621 typedef struct 1657 typedef struct
2877 UWORD8 t3; // FN modulo 51. 1913 UWORD8 t3; // FN modulo 51.
2878 UWORD8 tc; // Scell: TC 1914 UWORD8 tc; // Scell: TC
2879 UWORD8 fn_in_report; // FN modulo 102 or 104. 1915 UWORD8 fn_in_report; // FN modulo 102 or 104.
2880 UWORD16 fn_mod42432; // FN modulo 42432. 1916 UWORD16 fn_mod42432; // FN modulo 42432.
2881 UWORD8 fn_mod13; // FN modulo 13. 1917 UWORD8 fn_mod13; // FN modulo 13.
2882 UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4.
2883 #if L1_GPRS 1918 #if L1_GPRS
2884 UWORD8 fn_mod52; // FN modulo 52. 1919 UWORD8 fn_mod52; // FN modulo 52.
2885 UWORD8 fn_mod104; // FN modulo 104. 1920 UWORD8 fn_mod104; // FN modulo 104.
1921 UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4.
2886 UWORD32 block_id; // Block ID 1922 UWORD32 block_id; // Block ID
2887 #endif 1923 #endif
2888 } 1924 }
2889 T_TIME_INFO; 1925 T_TIME_INFO;
2890 1926
2980 UWORD32 qual_nbr_meas_sub; // Subset: nbr meas. of rxqual. 2016 UWORD32 qual_nbr_meas_sub; // Subset: nbr meas. of rxqual.
2981 UWORD8 dtx_used; // Set when DTX as been used in current reporting period. 2017 UWORD8 dtx_used; // Set when DTX as been used in current reporting period.
2982 } 2018 }
2983 T_SMEAS; 2019 T_SMEAS;
2984 2020
2985
2986 #if REL99
2987 #if FF_EMR
2988 typedef struct
2989 {
2990
2991 WORD16 rxlev_val_acc; // Accumulated value of RXLEV_VAL
2992 UWORD8 rxlev_val_nbr_meas; // Number of RXLEV_VAL value accumulated on block bases
2993 UWORD8 nbr_rcvd_blocks; // Number of correctly decoded blocks excluding SACCH FACCH etc Refer 05.08
2994 UWORD32 mean_bep_block_acc; // Accumulated value of MEAN_BEP
2995 UWORD16 cv_bep_block_acc; // Accumulated value of CV_BEP
2996 UWORD8 mean_bep_block_num; // Number of blocks over MEAN_BEP is accumulated.
2997 UWORD8 cv_bep_block_num; // Number of blocks over CV_BEP is accumulated.
2998 }
2999 T_SMEAS_EMR;
3000
3001 typedef struct
3002 {
3003 UWORD8 task; // task id (TCHTH, TCHTF, DDL, ADL, TCHA)
3004 UWORD8 burst_id; // burst ID only used for SDCCH.
3005 UWORD8 channel_mode; // channel mode in case of half / full rate
3006 UWORD8 subchannel; // subchannel number
3007 UWORD32 normalised_fn_mod13_mod4; // used to find block boundary in case of half rate
3008 BOOL facch_present; // necessary for processing to indicate reception of Facch
3009 BOOL facch_fire1; // necessary for processing to indicate good/bad reception of Facch
3010 UWORD8 a_ntd; // used for Data : FCS OK/FCS KO
3011 UWORD8 a_dd_0_blud; // check data/speech block presence on sub 0
3012 UWORD8 a_dd_0_bfi; // check data/speech block integrity on sub 0
3013 UWORD8 a_dd_1_blud; // check data/speech block presence on sub 1
3014 UWORD8 a_dd_1_bfi; // check data/speech block integrity on sub 1
3015 UWORD8 b_m1; // used for Data 14.4 M1 = 1 for second half block RLP
3016 UWORD8 b_f48blk_dl; // used for Data 4.8 : = 1 for second half block RLP
3017 UWORD8 b_ce; // used for Data : transparent / not transparent
3018 UWORD8 a_cd_fire1; // check SDCCH bloch integrity
3019 UWORD8 sid_present_sub0; // check sid present on sub 0
3020 UWORD8 sid_present_sub1; // check sid present on sub 1
3021 #if (AMR ==1)
3022 BOOL amr_facch_present; // necessary for AMR processing to indicate reception of Facch
3023 BOOL amr_facch_fire1; // necessary for AMR processing to indicate good/bad reception of Facch
3024 UWORD8 b_ratscch_blud; // check ratscch present
3025 UWORD8 ratscch_rxtype; // check type of AMR block
3026 UWORD8 amr_rx_type_sub0; // AMR type on sub 0
3027 UWORD8 amr_rx_type_sub1; // AMR type on sub 1
3028 #endif
3029 }
3030 T_EMR_PARAMS;
3031 #endif //FF_EMR
3032 #endif //REL99
3033
3034 /***************************************************************************************/ 2021 /***************************************************************************************/
3035 /* */ 2022 /* */
3036 /***************************************************************************************/ 2023 /***************************************************************************************/
3037 typedef struct 2024 typedef struct
3038 { 2025 {
3113 2100
3114 UWORD8 ms_ctrl; 2101 UWORD8 ms_ctrl;
3115 UWORD8 ms_ctrl_d; 2102 UWORD8 ms_ctrl_d;
3116 UWORD8 ms_ctrl_dd; 2103 UWORD8 ms_ctrl_dd;
3117 2104
3118 UWORD8 used_il [C_BA_PM_MEAS]; 2105 UWORD8 used_il [2];
3119 UWORD8 used_il_d [C_BA_PM_MEAS]; 2106 UWORD8 used_il_d [2];
3120 UWORD8 used_il_dd[C_BA_PM_MEAS]; 2107 UWORD8 used_il_dd[2];
3121 2108
3122 UWORD8 used_lna [C_BA_PM_MEAS]; 2109 UWORD8 used_lna [2];
3123 UWORD8 used_lna_d [C_BA_PM_MEAS]; 2110 UWORD8 used_lna_d [2];
3124 UWORD8 used_lna_dd[C_BA_PM_MEAS]; 2111 UWORD8 used_lna_dd[2];
3125 2112
3126 T_MEAS_INFO A[32+1]; // list of 32 neighbors + 1 serving. 2113 T_MEAS_INFO A[32+1]; // list of 32 neighbors + 1 serving.
3127 2114
3128 BOOL new_list_present; 2115 BOOL new_list_present;
3129 T_NEW_BA_LIST new_list; 2116 T_NEW_BA_LIST new_list;
3235 // For handover... 2222 // For handover...
3236 UWORD8 ho_acc; // Handover access (part of HO reference) 2223 UWORD8 ho_acc; // Handover access (part of HO reference)
3237 WORD32 ho_acc_to_send; // Set to 4 for SYNC HO and to -1 for ASYNC HO. 2224 WORD32 ho_acc_to_send; // Set to 4 for SYNC HO and to -1 for ASYNC HO.
3238 UWORD8 t3124; // Timer used in Async. Ho. 2225 UWORD8 t3124; // Timer used in Async. Ho.
3239 2226
3240 #if ((REL99 == 1) && (FF_BHO == 1))
3241 // For blind handover...
3242 BOOL report_time_diff;
3243 BOOL nci;
3244 UWORD8 real_time_difference;
3245 WORD32 HO_SignalCode;
3246 #endif
3247
3248 // For DPAGC algorithms purpose 2227 // For DPAGC algorithms purpose
3249 UWORD8 G_all[DPAGC_FIFO_LEN]; 2228 UWORD8 G_all[DPAGC_FIFO_LEN];
3250 UWORD8 G_DTX[DPAGC_FIFO_LEN]; 2229 UWORD8 G_DTX[DPAGC_FIFO_LEN];
3251 #if (AMR == 1) 2230 #if (AMR == 1)
3252 UWORD8 G_amr[DPAGC_AMR_FIFO_LEN]; 2231 UWORD8 G_amr[DPAGC_AMR_FIFO_LEN];
3297 BOOL pwrc; // Flag used to reject serving pwr meas. on beacon. 2276 BOOL pwrc; // Flag used to reject serving pwr meas. on beacon.
3298 2277
3299 BOOL handover_fail_mode; // Flag used to indicate that the L1 wait for an handover fail request 2278 BOOL handover_fail_mode; // Flag used to indicate that the L1 wait for an handover fail request
3300 #if (AMR == 1) 2279 #if (AMR == 1)
3301 BOOL sync_amr; // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB. 2280 BOOL sync_amr; // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB.
3302 #endif // (AMR == 1)
3303
3304 #if ((REL99 == 1) && (FF_BHO == 1))
3305 // For blind handover...
3306 BOOL handover_type;
3307 BOOL long_rem_handover_type;
3308 UWORD16 bcch_carrier_of_nbr_cell;
3309 UWORD32 fn_offset;
3310 UWORD32 time_alignment;
3311 #endif 2281 #endif
3312 } 2282 }
3313 T_DEDIC_PARAM; 2283 T_DEDIC_PARAM;
3314 2284
3315 /*************************************************************/ 2285 /*************************************************************/
3331 2301
3332 // flags and variables for wake-up .... 2302 // flags and variables for wake-up ....
3333 UWORD8 Os_ticks_required; // TRUE : Os ticks to recover 2303 UWORD8 Os_ticks_required; // TRUE : Os ticks to recover
3334 UWORD8 frame_adjust; // TRUE : adjust 1 frame 2304 UWORD8 frame_adjust; // TRUE : adjust 1 frame
3335 UWORD32 sleep_duration; // sleep duration computed at wakeup 2305 UWORD32 sleep_duration; // sleep duration computed at wakeup
3336 UWORD32 wakeup_time; // frame number of last wakeup
3337 UWORD16 wake_up_int_id; // Interrupt waking up the target
3338 UWORD8 wakeup_type; // Type of the interrupt
3339 UWORD8 why_big_sleep; // Type of the big sleep
3340 2306
3341 // flag for sleep .... 2307 // flag for sleep ....
3342 UWORD8 sleep_performed; // NONE,SMALL,BIG,DEEP,ALL 2308 UWORD8 sleep_performed; // NONE,SMALL,BIG,DEEP,ALL
3343 2309
3344 // status of clocks modules .... 2310 // status of clocks modules ....
3353 UWORD32 c_delta_hf_update; // UPDATE state 2319 UWORD32 c_delta_hf_update; // UPDATE state
3354 2320
3355 // trace gauging parameters 2321 // trace gauging parameters
3356 UWORD8 state; // state of the gauging 2322 UWORD8 state; // state of the gauging
3357 UWORD32 lf; // Number of the 32KHz 2323 UWORD32 lf; // Number of the 32KHz
3358 UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 ) 2324 UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 )
3359 UWORD32 root; // root & frac: the ratio of the HF & LF in each state. 2325 UWORD32 root; // root & frac: the ratio of the HF & LF in each state.
3360 UWORD32 frac; 2326 UWORD32 frac;
2327
3361 } 2328 }
3362 T_POWER_MNGT; 2329 T_POWER_MNGT;
3363 2330
3364 /*************************************************************/ 2331 /*************************************************************/
3365 /* code version structure... */ 2332 /* code version structure... */
3385 UWORD32 frame_count; 2352 UWORD32 frame_count;
3386 } 2353 }
3387 T_L1S_RECOVER; 2354 T_L1S_RECOVER;
3388 #endif 2355 #endif
3389 2356
3390 #if (TOA_ALGO == 2)
3391 typedef struct
3392 {
3393 WORD16 toa_shift; // TOA, value used to update the TOA
3394 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results.
3395 BOOL toa_update_flag; // FLAG used to indicate when to the TOA module when to update TOA.
3396 // NOTE: Flag set to TRUE in l1s_synch() and reset to FALSE in l1ctl_toa()
3397 UWORD16 toa_frames_counter; // TOA Frames counter - Number of the TDMA frames (or bursts) which are used for TOA
3398 // updation OR number of times l1ctl_toa() function is invoked
3399 // Reset every TOA_PERIOD_LEN[l1_mode] frames
3400 UWORD16 toa_accumul_counter; // Number of TDMA frames (or bursts) which are actually used for TOA tracking
3401 // <= toa_frames_counter, as only if SNR>0.46875 TOA estimated by DSP is used to
3402 // update the tracking algorithm
3403 WORD16 toa_accumul_value; // TOA_tracking_value accumulated over 'toa_accumul_counter' frames
3404 // Based on this value the shift to be applied is decided
3405 UWORD32 toa_update_fn; // a counter which is in direct relation to l1s.actual_time.fn
3406 // and used for TOA tracking in ALL MODES every 433 MF's (approx. 2 seconds)
3407
3408 }T_TOA_ALGO;
3409 #endif
3410
3411
3412 /***************************************************************************************/ 2357 /***************************************************************************************/
3413 /* L1S global variable structure... */ 2358 /* L1S global variable structure... */
3414 /***************************************************************************************/ 2359 /***************************************************************************************/
3415 typedef struct 2360 typedef struct
3416 { 2361 {
3438 2383
3439 // Control parameters... 2384 // Control parameters...
3440 //----------------------------------------- 2385 //-----------------------------------------
3441 UWORD32 afc_frame_count; // AFC, Frame count between 2 calls to afc control function. 2386 UWORD32 afc_frame_count; // AFC, Frame count between 2 calls to afc control function.
3442 WORD16 afc; // AFC, Common Frequency controle. 2387 WORD16 afc; // AFC, Common Frequency controle.
3443 #if (TOA_ALGO == 2)
3444 T_TOA_ALGO toa_var;
3445 #else
3446 WORD16 toa_shift; // TOA, value used to update the TOA 2388 WORD16 toa_shift; // TOA, value used to update the TOA
3447 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results. 2389 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results.
3448 2390
3449 UWORD16 toa_period_count; // TOA frame period used in PACKET TRANSFER MODE 2391 UWORD16 toa_period_count; // TOA frame period used in PACKET TRANSFER MODE
3450 BOOL toa_update; // TOA, is set at the end of the update period, toa update occurs on next valid frame 2392 BOOL toa_update; // TOA, is set at the end of the update period, toa update occurs on next valid frame
3451 #endif
3452 2393
3453 // Flag registers for RF task controle... 2394 // Flag registers for RF task controle...
3454 //----------------------------------------- 2395 //-----------------------------------------
3455 // Made these control registers short's as more than 8-bits required. 2396 // Made these control registers short's as more than 8-bits required.
3456 UWORD16 tpu_ctrl_reg; // (x,x,x,x,SYNC,RX,TX,MS) RX/TX/MS/SYNC bit ON whenever an 2397 UWORD16 tpu_ctrl_reg; // (x,x,x,x,SYNC,RX,TX,MS) RX/TX/MS/SYNC bit ON whenever an
3491 #if L2_L3_SIMUL 2432 #if L2_L3_SIMUL
3492 // GTT test 2433 // GTT test
3493 T_GTT_TEST_L1S gtt_test; 2434 T_GTT_TEST_L1S gtt_test;
3494 #endif 2435 #endif
3495 #endif 2436 #endif
3496 #if (L1_DYN_DSP_DWNLD == 1) 2437
3497 UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager 2438 #if (L1_DYN_DSP_DWNLD == 1)
3498 #endif // L1_DYN_DSP_DWNLD 2439 UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager
2440 #endif
3499 #if (AUDIO_TASK == 1) 2441 #if (AUDIO_TASK == 1)
3500 // Audio task. 2442 // Audio task.
3501 //----------------------------------------- 2443 //-----------------------------------------
3502 BOOL l1_audio_it_com; // Flag to enable the ITCOM. 2444 BOOL l1_audio_it_com; // Flag to enable the ITCOM.
3503 UWORD8 audio_state[NBR_AUDIO_MANAGER]; // state for L1S audio manager. 2445 UWORD8 audio_state[NBR_AUDIO_MANAGER]; // state for L1S audio manager.
3506 T_L1S_MELODY_TASK melody1; 2448 T_L1S_MELODY_TASK melody1;
3507 #endif 2449 #endif
3508 #if (VOICE_MEMO) 2450 #if (VOICE_MEMO)
3509 T_L1S_VM_TASK voicememo; 2451 T_L1S_VM_TASK voicememo;
3510 #endif 2452 #endif
3511 #if (L1_PCM_EXTRACTION)
3512 T_L1S_PCM_TASK pcm;
3513 #endif
3514 #if (L1_VOICE_MEMO_AMR) 2453 #if (L1_VOICE_MEMO_AMR)
3515 T_L1S_VM_AMR_TASK voicememo_amr; 2454 T_L1S_VM_AMR_TASK voicememo_amr;
3516 #endif 2455 #endif
3517 #if (SPEECH_RECO) 2456 #if (SPEECH_RECO)
3518 T_L1S_SR_TASK speechreco; 2457 T_L1S_SR_TASK speechreco;
3519 #endif 2458 #endif
3520 #if (L1_AEC == 1) 2459 #if (AEC)
3521 T_L1S_AEC_TASK aec; 2460 T_L1S_AEC_TASK aec;
3522 #endif 2461 #endif
3523 #if (MELODY_E2) 2462 #if (MELODY_E2)
3524 T_L1S_MELODY_E2_COMMON_VAR melody_e2; 2463 T_L1S_MELODY_E2_COMMON_VAR melody_e2;
3525 T_L1S_MELODY_E2_TASK melody0_e2; 2464 T_L1S_MELODY_E2_TASK melody0_e2;
3526 T_L1S_MELODY_E2_TASK melody1_e2; 2465 T_L1S_MELODY_E2_TASK melody1_e2;
3527 #endif 2466 #endif
3528 #if (L1_EXT_AUDIO_MGT == 1)
3529 T_L1S_EXT_AUDIO_MGT_VAR ext_audio_mgt;
3530 #endif
3531 #if (L1_WCM == 1)
3532 T_WCM_ACTION wcm_action;
3533 #endif
3534 #if (L1_AGC_UL == 1)
3535 T_AGC_ACTION agc_ul_action;
3536 #endif
3537 #if (L1_AGC_DL == 1)
3538 T_AGC_ACTION agc_dl_action;
3539 #endif
3540 #if (L1_ANR == 2)
3541 T_ANR_ACTION anr_ul_action;
3542 #endif
3543 #if (L1_IIR == 2)
3544 T_IIR_ACTION iir_dl_action;
3545 #endif
3546 #if (L1_DRC == 1)
3547 T_DRC_ACTION drc_dl_action;
3548 #endif
3549
3550 #endif 2467 #endif
3551 2468
3552 UWORD8 last_used_txpwr; 2469 UWORD8 last_used_txpwr;
3553 2470
3554 #if L1_GPRS 2471 #if L1_GPRS
3555 BOOL ctrl_synch_before; //control of synchro for CCCH reading en TN-2 2472 BOOL ctrl_synch_before; //control of synchro for CCCH reading en TN-2
3556 UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle
3557 #endif 2473 #endif
3558 2474
3559 #if L1_RECOVERY 2475 #if L1_RECOVERY
3560 T_L1S_RECOVER recovery; 2476 T_L1S_RECOVER recovery;
3561 #endif 2477 #endif
3562 BOOL spurious_fb_detected; 2478 BOOL spurious_fb_detected;
3563 2479
3564 // Handling DTX mode 2480 // Handling DTX mode
3565 BOOL dtx_ul_on; //earlier name was- dtx_on 2481 BOOL dtx_ul_on;
3566 WORD8 facch_bursts; 2482 WORD8 facch_bursts;
2483
3567 // DTX mode in AMR 2484 // DTX mode in AMR
3568 BOOL dtx_amr_dl_on; // set to TRUE when the AMR is in DTX mode in downlink 2485 BOOL dtx_amr_dl_on; // set to TRUE when the AMR is in DTX mode in downlink
3569 2486
3570 //+++++++++++++++++
3571 // GSM IDLE IN RAM
3572 //+++++++++++++++++
3573
3574 #if (GSM_IDLE_RAM != 0)
3575 T_L1S_GSM_IDLE_INTRAM gsm_idle_ram_ctl;
3576
3577 #if (GSM_IDLE_RAM == 1)
3578 // Used to avoid allocation of ext mem data while in L1S_meas_manager (allocate signal long time before sending)
3579 T_RXLEV_MEAS A[8];
3580 #endif
3581 #endif
3582
3583 //+++++++++++++++++
3584 // Triton Audio ON/OFF Changes
3585 //+++++++++++++++++
3586 #if (L1_AUDIO_MCU_ONOFF == 1)
3587 T_L1S_AUDIO_ONOFF_MANAGER audio_on_off_ctl;
3588 #endif
3589
3590 #if (ANALOG == 11)
3591 UWORD8 abb_write_done;
3592 #endif
3593 UWORD8 tcr_prog_done;
3594
3595 #if (L1_RF_KBD_FIX == 1)
3596 UWORD16 total_kbd_on_time;
3597 UWORD8 correction_ratio; //KPD_CORRECTION_RATIO correction_ratio;//omaps00090550
3598 #endif
3599 #if (L1_GPRS == 1)
3600 BOOL algo_change_synchro_active;
3601 #endif /* FF_L1_FAST_DECODING */
3602 #if (FF_REPEATED_SACCH == 1)
3603 // Repeated SACCH mode
3604 T_REPEAT_SACCH repeated_sacch;
3605 #endif /* FF_REPEATED_SACCH */
3606 #if (FF_REPEATED_DL_FACCH == 1)
3607 // Repeated FACCH mode
3608 T_REPEAT_FACCH repeated_facch;
3609 #endif /* FF_REPEATED_DL_FACCH == 1 */
3610 /* 0 indicates success, non zero value indicates failure */
3611 UWORD8 boot_result;
3612 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
3613 UWORD8 force_gauging_next_paging_due_to_CCHR;
3614
3615 } 2487 }
3616 T_L1S_GLOBAL; 2488 T_L1S_GLOBAL;
3617 2489
3618 #if (AUDIO_TASK == 1)
3619 #if (L1_VOCODER_IF_CHANGE == 1)
3620 typedef struct
3621 {
3622 BOOL enabled; // TRUE if enabled, FALSE if disabled
3623 BOOL automatic_disable; // TRUE if vocoders are automatically disabld via a MPHC_STOP_DEDICATED_REQ, FALSE otherwise.
3624 } T_L1A_VOCODER_CFG_GLOBAL;
3625 #endif // L1_VOCODER_IF_CHANGE == 1
3626 typedef struct
3627 {
3628 UWORD8 outen1;
3629 UWORD8 outen2;
3630 UWORD8 outen3;
3631 UWORD8 classD;
3632 UWORD8 command_requested; /* updated in L1a task context*/
3633 UWORD8 command_commited; /* updated in I2c ISR callback context*/
3634 } T_OUTEN_CFG_TASK;
3635
3636 #endif // AUDIO_TASK == 1
3637 /***************************************************************************************/ 2490 /***************************************************************************************/
3638 /* L1A global variable structure... */ 2491 /* L1A global variable structure... */
3639 /***************************************************************************************/ 2492 /***************************************************************************************/
3640 typedef struct 2493 typedef struct
3641 { 2494 {
3649 2502
3650 // Flag for forward/delete message management. 2503 // Flag for forward/delete message management.
3651 //--------------------------------------------- 2504 //---------------------------------------------
3652 UWORD8 l1_msg_forwarded; 2505 UWORD8 l1_msg_forwarded;
3653 2506
3654 #if (L1_DYN_DSP_DWNLD == 1) 2507 #if (L1_DYN_DSP_DWNLD == 1)
3655 // Dynamic donload global variables 2508 // Dynamic donload global variables
3656 T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld; 2509 T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld;
3657 #endif 2510 #endif
3658
3659 // New Vocoder IF global L1A variable: L1A checks if the vocoder has already been enabled/disabled
3660 // in order to robust to possible multiples enabling/disabling messages coming from PS
3661
3662 #if (L1_VOCODER_IF_CHANGE == 1)
3663 T_L1A_VOCODER_CFG_GLOBAL vocoder_state;
3664 #endif // L1_VOCODER_IF_CHANGE == 1
3665 2511
3666 // signal code indicating the reason of L1C_DEDIC_DONE 2512 // signal code indicating the reason of L1C_DEDIC_DONE
3667 UWORD32 confirm_SignalCode; 2513 UWORD32 confirm_SignalCode;
3668 2514
3669 #if (L1_MP3 == 1) 2515 // Trace the best frequencies reported in MPHC_RXLEV_IND
3670 T_L1_MP3_L1A mp3_task; 2516 #if (L1_MPHC_RXLEV_IND_REPORT_SORT==1)
3671 //ADDED FOR AAC 2517 UWORD16 tab_index[MAX_MEAS_RXLEV_IND_TRACE];
2518 UWORD16 max_report; //max number of fq reported, can be < MAX_MEAS_RXLEV_IND_TRACE if list is smaller
3672 #endif 2519 #endif
3673
3674 #if (L1_AAC == 1)
3675 T_L1_AAC_L1A aac_task;
3676 #endif
3677 #if(L1_IIR == 2)
3678 xSignalHeaderRec *iir_req_msg_ptr;
3679 #endif
3680
3681 #if(L1_DRC == 1)
3682 xSignalHeaderRec *drc_req_msg_ptr;
3683 #endif
3684
3685 #if(L1_WCM == 1)
3686 xSignalHeaderRec *wcm_req_msg_ptr;
3687 #endif
3688
3689 #if(L1_CHECK_COMPATIBLE == 1)
3690 BOOL vcr_wait;
3691 BOOL stop_req;
3692 BOOL vcr_msg_param;
3693 BOOL vch_auto_disable;
3694 #endif
3695
3696 } 2520 }
3697 T_L1A_GLOBAL; 2521 T_L1A_GLOBAL;
3698 2522
3699 /***************************************************************************************/ 2523 /***************************************************************************************/
3700 /* L1A -> L1S communication structure... */ 2524 /* L1A -> L1S communication structure... */
3718 T_BCCHS nbcchs; 2542 T_BCCHS nbcchs;
3719 T_BCCHS ebcchs; 2543 T_BCCHS ebcchs;
3720 2544
3721 // Synchro information. 2545 // Synchro information.
3722 //--------------------------------------- 2546 //---------------------------------------
3723 #if L1_FF_WA_OMAPS00099442
3724 BOOL change_tpu_offset_flag;
3725 #endif
3726
3727 WORD8 tn_difference; // Timeslot difference for next synchro. 2547 WORD8 tn_difference; // Timeslot difference for next synchro.
3728 UWORD8 dl_tn; // Current timeslot for downlink stuffs. 2548 UWORD8 dl_tn; // Current timeslot for downlink stuffs.
3729 #if L1_GPRS 2549 #if L1_GPRS
3730 UWORD8 dsp_scheduler_mode; // DSP Scheduler mode (GPRS or GSM). 2550 UWORD8 dsp_scheduler_mode; // DSP Scheduler mode (GPRS or GSM).
3731 #endif 2551 #endif
3766 UWORD8 adc_traffic_period; 2586 UWORD8 adc_traffic_period;
3767 UWORD8 adc_cpt; 2587 UWORD8 adc_cpt;
3768 2588
3769 // TXPWR management. 2589 // TXPWR management.
3770 //------------------- 2590 //-------------------
3771 #if (L1_FF_MULTIBAND == 0)
3772 UWORD8 powerclass_band1; // Power class for the MS, given in ACCESS LINK mode (GSM Band). 2591 UWORD8 powerclass_band1; // Power class for the MS, given in ACCESS LINK mode (GSM Band).
3773 UWORD8 powerclass_band2; // Power class for the MS, given in ACCESS LINK mode (DCS Band). 2592 UWORD8 powerclass_band2; // Power class for the MS, given in ACCESS LINK mode (DCS Band).
3774 #else
3775 UWORD8 powerclass[RF_NB_SUPPORTED_BANDS];
3776 #endif
3777
3778 2593
3779 // Dedicated parameters. 2594 // Dedicated parameters.
3780 //---------------------- 2595 //----------------------
3781 T_DEDIC_PARAM dedic_set; // Dedicated channel parameters. 2596 T_DEDIC_PARAM dedic_set; // Dedicated channel parameters.
3782 2597
3790 // BA list / FULL list. 2605 // BA list / FULL list.
3791 //--------------------- 2606 //---------------------
3792 T_BA_LIST ba_list; 2607 T_BA_LIST ba_list;
3793 T_FULL_LIST full_list; 2608 T_FULL_LIST full_list;
3794 T_FULL_LIST_MEAS *full_list_ptr; 2609 T_FULL_LIST_MEAS *full_list_ptr;
3795
3796 #if ((REL99 == 1) && (FF_BHO == 1))
3797 // For blind handover...
3798 T_BHO_PARAM nsync_fbsb;
3799 #endif
3800 2610
3801 //+++++++++++++++++++ 2611 //+++++++++++++++++++
3802 // L1S scheduler... 2612 // L1S scheduler...
3803 //+++++++++++++++++++ 2613 //+++++++++++++++++++
3804 2614
3845 T_MELODY_TASK melody1_task; 2655 T_MELODY_TASK melody1_task;
3846 #endif 2656 #endif
3847 #if (VOICE_MEMO) 2657 #if (VOICE_MEMO)
3848 T_VM_TASK voicememo_task; 2658 T_VM_TASK voicememo_task;
3849 #endif 2659 #endif
3850 #if (L1_PCM_EXTRACTION)
3851 T_PCM_TASK pcm_task;
3852 #endif
3853 #if (L1_VOICE_MEMO_AMR) 2660 #if (L1_VOICE_MEMO_AMR)
3854 T_VM_AMR_TASK voicememo_amr_task; 2661 T_VM_AMR_TASK voicememo_amr_task;
3855 #endif 2662 #endif
3856 #if (SPEECH_RECO) 2663 #if (SPEECH_RECO)
3857 T_SR_TASK speechreco_task; 2664 T_SR_TASK speechreco_task;
3858 #endif 2665 #endif
3859 #if (L1_AEC == 1) 2666 #if (AEC)
3860 T_AEC_TASK aec_task;
3861 #endif
3862 #if (L1_AEC == 2)
3863 T_AEC_TASK aec_task; 2667 T_AEC_TASK aec_task;
3864 #endif 2668 #endif
3865 #if (FIR) 2669 #if (FIR)
3866 T_FIR_TASK fir_task; 2670 T_FIR_TASK fir_task;
3867 #endif 2671 #endif
3873 T_MELODY_E2_TASK melody1_e2_task; 2677 T_MELODY_E2_TASK melody1_e2_task;
3874 #endif 2678 #endif
3875 #if (L1_CPORT == 1) 2679 #if (L1_CPORT == 1)
3876 T_CPORT_TASK cport_task; 2680 T_CPORT_TASK cport_task;
3877 #endif 2681 #endif
3878 2682 #endif
3879 #if (L1_EXTERNAL_AUDIO_VOICE_ONOFF == 1 || L1_EXT_MCU_AUDIO_VOICE_ONOFF == 1)
3880 T_AUDIO_ONOFF_TASK audio_onoff_task;
3881 #endif
3882
3883 BOOL audio_forced_by_l1s; /* This value is used to indicate if the L1S is forcing the audio_on_off feature in the DSP CQ21718 */
3884
3885 #if (L1_STEREOPATH == 1)
3886 T_STEREOPATH_DRV_TASK stereopath_drv_task;
3887 #endif
3888
3889 #if (L1_MP3 == 1)
3890 T_MP3_TASK mp3_task;
3891 #endif
3892
3893 #if (L1_MIDI == 1)
3894 T_MIDI_TASK midi_task;
3895 #endif
3896 //ADDED FOR AAC
3897 #if (L1_AAC == 1)
3898 T_AAC_TASK aac_task;
3899 #endif
3900
3901 #if (L1_ANR == 1)
3902 T_ANR_TASK anr_task;
3903 #endif
3904
3905 #if (L1_ANR == 2)
3906 T_AQI_ANR_TASK anr_task;
3907 #endif
3908
3909 #if (L1_IIR == 1)
3910 T_IIR_TASK iir_task;
3911 #endif
3912
3913 #if (L1_AGC_UL == 1)
3914 T_AQI_AGC_UL_TASK agc_ul_task;
3915 #endif
3916
3917 #if (L1_AGC_DL == 1)
3918 T_AQI_AGC_DL_TASK agc_dl_task;
3919 #endif
3920
3921 #if (L1_IIR == 2)
3922 T_AQI_IIR_TASK iir_task;
3923 #endif
3924
3925 #if (L1_DRC == 1)
3926 T_AQI_DRC_TASK drc_task;
3927 #endif
3928
3929 #if (L1_LIMITER == 1)
3930 T_LIMITER_TASK limiter_task;
3931 #endif
3932
3933 #if (L1_ES == 1)
3934 T_ES_TASK es_task;
3935 #endif
3936
3937 #if (L1_WCM == 1)
3938 T_AQI_WCM_TASK wcm_task;
3939 #endif
3940
3941 //++++++++++++++++++++++++++++++++++++
3942 // Fake L1S sm for audio IT generation
3943 //++++++++++++++++++++++++++++++++++++
3944 T_AUDIOIT_TASK audioIt_task;
3945
3946 /*
3947 * FreeCalypso change: I had to move this part here, or else
3948 * compilation fails w/o AUDIO_TASK
3949 */
3950 T_OUTEN_CFG_TASK outen_cfg_task;
3951 #endif
3952
3953 2683
3954 //+++++++++++++ 2684 //+++++++++++++
3955 // GTT task 2685 // GTT task
3956 //+++++++++++++ 2686 //+++++++++++++
3957 2687
3958 #if (L1_GTT == 1) 2688 #if (L1_GTT == 1)
3959 T_GTT_TASK gtt_task; 2689 T_GTT_TASK gtt_task;
3960 #endif 2690 #endif
3961 2691
3962 // Dynamic DSP download task 2692 // Dynamic DSP download task
3963 #if (L1_DYN_DSP_DWNLD == 1) 2693 #if (L1_DYN_DSP_DWNLD == 1)
3964 T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task; 2694 T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task;
3965 #endif 2695 #endif
3966
3967 #if REL99
3968 #if FF_EMR
3969 T_SMEAS_EMR Smeas_dedic_emr;
3970 #endif
3971 #endif
3972
3973 #if (FF_L1_FAST_DECODING == 1)
3974 UWORD8 last_fast_decoding;
3975 #endif /* if (FF_L1_FAST_DECODING == 1) */
3976 2696
3977 } 2697 }
3978 T_L1A_L1S_COM; 2698 T_L1A_L1S_COM;
3979 2699
3980 /***************************************************************************************/ 2700 /***************************************************************************************/
3986 UWORD8 dsp_r_page; // Active page for ARM "reading" from DSP {0,1}. 2706 UWORD8 dsp_r_page; // Active page for ARM "reading" from DSP {0,1}.
3987 UWORD8 dsp_r_page_used; // Used in "l1_synch" to know if the read page must be chged. 2707 UWORD8 dsp_r_page_used; // Used in "l1_synch" to know if the read page must be chged.
3988 2708
3989 T_DB_DSP_TO_MCU *dsp_db_r_ptr; // MCU<->DSP comm. read page (Double Buffered comm. memory). 2709 T_DB_DSP_TO_MCU *dsp_db_r_ptr; // MCU<->DSP comm. read page (Double Buffered comm. memory).
3990 T_DB_MCU_TO_DSP *dsp_db_w_ptr; // MCU<->DSP comm. write page (Double Buffered comm. memory). 2710 T_DB_MCU_TO_DSP *dsp_db_w_ptr; // MCU<->DSP comm. write page (Double Buffered comm. memory).
3991 #if (DSP ==38) || (DSP == 39)
3992 T_DB_COMMON_MCU_TO_DSP *dsp_db_common_w_ptr; // MCU<->DSP comm. common write page (Double Buffered comm. memory).
3993 #endif
3994 T_NDB_MCU_DSP *dsp_ndb_ptr; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory). 2711 T_NDB_MCU_DSP *dsp_ndb_ptr; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
3995 2712
3996 T_PARAM_MCU_DSP *dsp_param_ptr; // MCU<->DSP comm. read/write (Param comm. memory). 2713 T_PARAM_MCU_DSP *dsp_param_ptr; // MCU<->DSP comm. read/write (Param comm. memory).
3997 2714
3998 #if (DSP_DEBUG_TRACE_ENABLE == 1) 2715 #if (DSP_DEBUG_TRACE_ENABLE == 1)
3999 T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr; 2716 T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr;
4000 T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr; 2717 T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr;
4001 #endif 2718 #endif
4002
4003 /* DSP CPU load measurement */
4004 /* FreeCalypso change: the necessary #if was missing */
4005 #if (DSP == 38) || (DSP == 39)
4006 T_DB_MCU_TO_DSP_CPU_LOAD *dsp_cpu_load_db_w_ptr;
4007 #endif
4008 } 2719 }
4009 T_L1S_DSP_COM; 2720 T_L1S_DSP_COM;
4010 2721
4011 /***************************************************************************************/ 2722 /***************************************************************************************/
4012 /* L1A -> TPU communication structure... */ 2723 /* L1A -> TPU communication structure... */
4026 T_L1S_TPU_COM; 2737 T_L1S_TPU_COM;
4027 2738
4028 /***************************************************************************************/ 2739 /***************************************************************************************/
4029 /* L1 configuration structure */ 2740 /* L1 configuration structure */
4030 /***************************************************************************************/ 2741 /***************************************************************************************/
4031 #if (L1_FF_MULTIBAND == 0)
4032 2742
4033 typedef struct 2743 typedef struct
4034 { 2744 {
4035 UWORD8 id; //standard identifier 2745 UWORD8 id; //standard identifier
4036 2746
4062 UWORD16 lna_switch_thr_high_band1; 2772 UWORD16 lna_switch_thr_high_band1;
4063 UWORD16 lna_switch_thr_high_band2; 2773 UWORD16 lna_switch_thr_high_band2;
4064 } 2774 }
4065 T_L1_STD_CNFG; 2775 T_L1_STD_CNFG;
4066 2776
4067 #endif // #if (L1_FF_MULTIBAND == 0)
4068
4069 #if (L1_FF_MULTIBAND == 1)
4070
4071 #if 0
4072 typedef struct
4073 {
4074 UWORD16 nbmax_carrier;
4075 UWORD16 first_radio_freq;
4076 UWORD16 first_tpu_radio_freq;
4077 UWORD16 first_operative_radio_freq;
4078 UWORD8 physical_band_id;
4079 }
4080 T_MULTIBAND_CONVERSION_DATA;
4081
4082 typedef struct
4083 {
4084 UWORD16 lna_switch_thr_high;
4085 UWORD16 lna_switch_thr_low;
4086 UWORD16 lna_att;
4087 UWORD16 g_magic;
4088 UWORD8 swap_iq;
4089 UWORD16 cal_freq1;
4090 UWORD8 tx_turning_point;
4091 UWORD8 max_txpwr;
4092 UWORD8 gsm_band_identifier;
4093 }
4094 T_MULTIBAND_RF_DATA;
4095 #endif // if 0
4096 typedef struct
4097 {
4098 UWORD8 radio_band;
4099 UWORD8 power_class;
4100 UWORD8 _align0;
4101 UWORD8 _align1;
4102 }
4103 T_L1_MULTIBAND_POWER_CLASS;
4104
4105
4106 #endif /*if (L1_FF_MULTIBAND == 1)*/
4107
4108
4109 //RF dependent parameter definitions 2777 //RF dependent parameter definitions
4110 typedef struct 2778 typedef struct
4111 { 2779 {
4112 UWORD16 rx_synth_setup_time; 2780 UWORD16 rx_synth_setup_time;
4113 UWORD8 rx_synth_load_split; 2781 UWORD8 rx_synth_load_split;
4141 UWORD16 il_min; 2809 UWORD16 il_min;
4142 2810
4143 UWORD16 fixed_txpwr; 2811 UWORD16 fixed_txpwr;
4144 WORD16 eeprom_afc; 2812 WORD16 eeprom_afc;
4145 WORD8 setup_afc_and_rf; 2813 WORD8 setup_afc_and_rf;
4146 WORD8 rf_wakeup_tpu_scenario_duration; // Duration (in TDMA frames) of TPU scenario for RF wakeup
4147 2814
4148 UWORD32 psi_sta_inv; 2815 UWORD32 psi_sta_inv;
4149 UWORD32 psi_st; 2816 UWORD32 psi_st;
4150 UWORD32 psi_st_32; 2817 UWORD32 psi_st_32;
4151 UWORD32 psi_st_inv; 2818 UWORD32 psi_st_inv;
4219 UWORD16 vaud_cfg; 2886 UWORD16 vaud_cfg;
4220 UWORD16 vauo_onoff; 2887 UWORD16 vauo_onoff;
4221 UWORD16 vaus_vol; 2888 UWORD16 vaus_vol;
4222 UWORD16 vaud_pll; 2889 UWORD16 vaud_pll;
4223 #endif 2890 #endif
4224 #if (ANALOG == 11) 2891
4225 UWORD8 vulgain;
4226 UWORD8 vdlgain;
4227 UWORD8 sidetone;
4228 UWORD8 ctrl1;
4229 UWORD8 ctrl2;
4230 UWORD8 ctrl3;
4231 UWORD8 ctrl4;
4232 UWORD8 ctrl5;
4233 UWORD8 ctrl6;
4234 UWORD8 popauto;
4235 UWORD8 outen1;
4236 UWORD8 outen2;
4237 UWORD8 outen3;
4238 UWORD8 aulga;
4239 UWORD8 aurga;
4240 #endif
4241 #if (RF_FAM == 61)
4242 UWORD16 apcdel1;
4243 UWORD16 apcdel2;
4244 UWORD16 apcctrl2;
4245 #endif
4246 #if L1_GPRS 2892 #if L1_GPRS
4247 UWORD16 toa_pm_thres; // PM threshold for TOA algorithm feeding in packet transfer mode 2893 UWORD16 toa_pm_thres; // PM threshold for TOA algorithm feeding in packet transfer mode
4248 #endif 2894 #endif
4249 } 2895 }
4250 T_L1_PARAMS; 2896 T_L1_PARAMS;
4251 2897
4252 typedef struct 2898 typedef struct
4253 { 2899 {
4254 #if (L1_FF_MULTIBAND == 0) 2900 T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT
4255 T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT 2901 UWORD8 pwr_mngt; //power management active
4256 #endif // L1_FF_MULTIBAND == 0 2902 UWORD8 tx_pwr_code;
4257 2903 UWORD16 dwnld;
4258 UWORD8 pwr_mngt; //power management active 2904 T_L1_PARAMS params;
4259 UWORD8 tx_pwr_code; 2905 double dpll; //dpll factor
4260 #if IDS 2906
4261 UWORD8 ids_enable; 2907 #if TESTMODE
2908 //Define the TestMode flag and TestMode parameters
2909 UWORD8 TestMode;
2910
2911 UWORD8 agc_enable;
2912 UWORD8 afc_enable;
2913 UWORD8 adc_enable;
2914
2915 T_TM_PARAMS tmode; //TestMode parameters structure
2916 #endif
2917
2918 }
2919 T_L1_CONFIG;
2920
2921 /***************************************************************************************/
2922 /* API HISR -> L1A communication structure... Defined in case dynamic download is defined */
2923 /***************************************************************************************/
2924 /***************************************************************************************/
2925 /* Global API HISR -Defined in case dynamic download is defined
2926 /***************************************************************************************/
2927
2928
2929 #if(L1_DYN_DSP_DWNLD==1)
2930 typedef struct
2931 {
2932 T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld;
2933 } T_L1A_API_HISR_COM;
2934
2935 typedef struct
2936 {
2937 T_L1_DYN_DWNLD_API_HISR dyn_dwnld;
2938 } T_L1_API_HISR;
4262 #endif 2939 #endif
4263 UWORD16 dwnld;
4264 T_L1_PARAMS params;
4265 double dpll; //dpll factor
4266
4267 #if TESTMODE
4268 //Define the TestMode flag and TestMode parameters
4269 UWORD8 TestMode;
4270
4271 UWORD8 agc_enable;
4272 UWORD8 afc_enable;
4273 UWORD8 adc_enable;
4274 #if (FF_REPEATED_SACCH == 1)
4275 UWORD8 repeat_sacch_enable;
4276 #endif /* FF_REPEATED_SACCH == 1 */
4277 #if (FF_REPEATED_DL_FACCH == 1)
4278 UWORD8 repeat_facch_dl_enable;
4279 #endif /* (FF_REPEATED_DL_FACCH == 1)*/
4280
4281 T_TM_PARAMS tmode; //TestMode parameters structure
4282 #endif
4283
4284 T_FACCH_TEST_PARAMS facch_test;
4285 }
4286 T_L1_CONFIG;
4287 // SAPI identifier : 0 (Signalling), 3 (Short Messages Services)
4288 #if FF_REPEATED_SACCH
4289 typedef enum
4290 {
4291 SAPI_0 = 0,
4292 SAPI_3 = 3
4293 } T_L1_SAPI_ID;
4294 #endif /* FF_REPEATED_SACCH */
4295
4296 /***************************************************************************************/
4297 /* API HISR -> L1A communication structure... */
4298 /***************************************************************************************/
4299 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1) ) // equivalent to an API_HISR flag
4300
4301 #if FF_L1_IT_DSP_USF
4302 typedef struct
4303 {
4304 // Fast USF HISR pending
4305 BOOL pending;
4306 } T_L1A_USF_HISR_COM;
4307 #endif
4308
4309 #if FF_L1_IT_DSP_DTX
4310 typedef struct
4311 {
4312 // Fast DTX HISR pending
4313 BOOL pending;
4314 // TX activity programmed in TCH block
4315 BOOL tx_active;
4316 // Fast DTX service is available
4317 BOOL fast_dtx_ready;
4318 // Fast DTX service latency timer
4319 UWORD8 fast_dtx_ready_timer;
4320 // Fast DTX state variable
4321 UWORD8 dtx_status;
4322 } T_L1A_DTX_HISR_COM;
4323 #endif
4324
4325 #if (FF_L1_FAST_DECODING == 1)
4326 typedef struct
4327 {
4328 /* Fast Decoding HISR pending */
4329 BOOL pending;
4330 /* Current CRC */
4331 BOOL crc_error;
4332 /* Status (IT awaited?) */
4333 UWORD8 status;
4334 /* Control required during incoming fast API IT? */
4335 BOOL deferred_control_req;
4336 /* Task using fast decoding */
4337 UWORD8 task;
4338 /* Burst ID of the task */
4339 UWORD8 burst_id;
4340 /* Is the decoding of a contiguous block starting? */
4341 BOOL contiguous_decoding;
4342 } T_L1A_FAST_DECODING_HISR_COM;
4343 #endif /* FF_L1_FAST_DECODING */
4344
4345 typedef struct
4346 {
4347 #if (L1_MP3 == 1)
4348 T_L1A_MP3_HISR_COM mp3;
4349 #endif
4350 #if (L1_MIDI == 1)
4351 T_L1A_MIDI_HISR_COM midi;
4352 //ADDED FOR AAC
4353 #endif
4354 #if (L1_AAC == 1)
4355 T_L1A_AAC_HISR_COM aac;
4356 #endif
4357 #if (L1_DYN_DSP_DWNLD == 1)
4358 T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld;
4359 #endif // L1_DYN_DSP_DWNLD
4360 #if (FF_L1_IT_DSP_USF == 1)
4361 T_L1A_USF_HISR_COM usf;
4362 #endif
4363 #if (FF_L1_IT_DSP_DTX == 1)
4364 T_L1A_DTX_HISR_COM dtx;
4365 #endif
4366 #if (FF_L1_FAST_DECODING == 1)
4367 T_L1A_FAST_DECODING_HISR_COM fast_decoding;
4368 #endif /* FF_L1_FAST_DECODING */
4369 } T_L1A_API_HISR_COM;
4370
4371 #if (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1)
4372 typedef struct
4373 {
4374 #if (L1_MP3 == 1)
4375 T_L1_MP3_API_HISR mp3;
4376 #endif
4377 #if (L1_MIDI == 1)
4378 T_L1_MIDI_API_HISR midi;
4379 #endif
4380 //ADDED FOR AAC
4381 #if (L1_AAC == 1)
4382 T_L1_AAC_API_HISR aac;
4383 #endif
4384 #if (L1_DYN_DSP_DWNLD == 1)
4385 T_L1_DYN_DWNLD_API_HISR dyn_dwnld;
4386 #endif // L1_DYN_DSP_DWNLD
4387 } T_L1_API_HISR;
4388 #endif // #if (L1_MP3 == 1) || (L1_MIDI == 1) || || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1)
4389
4390 #endif //(L1_MP3 == 1) || (L1_MIDI == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1)
4391
4392 typedef struct
4393 {
4394 /* 0 indicates success 1 indicates failure */
4395 UWORD16 boot_result;
4396 UWORD16 drp_maj_ver;
4397 UWORD16 drp_min_ver;
4398 // MCU versions
4399 UWORD16 mcu_tcs_program_release;
4400 UWORD16 mcu_tcs_official;
4401 UWORD16 mcu_tcs_internal;
4402 // DSP versions & checksum
4403 UWORD16 dsp_code_version;
4404 UWORD16 dsp_patch_version;
4405 }T_L1_BOOT_VERSION_CODE;
4406
4407