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comparison L1/include/l1_confg.h @ 3:f93dab57b032

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L1/include: TCS211-based version restored
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:45:00 +0000
parents 75a11d740a02
children 5fd4e7669c93
comparison
equal deleted inserted replaced
2:7c13c26f1aa4 3:f93dab57b032
1 /************* Revision Controle System Header ************* 1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software 2 * GSM Layer 1 software
3 * L1_CONFG.H 3 * L1_CONFG.H
4 * 4 *
5 * Filename l1_confg.h 5 * Filename l1_confg.h
6 * Copyright 2003 (C) Texas Instruments 6 * Copyright 2003 (C) Texas Instruments
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9 9
10 #ifndef __L1_CONFG_H__ 10 #ifndef __L1_CONFG_H__
11 #define __L1_CONFG_H__ 11 #define __L1_CONFG_H__
30 // Code Version possible choices 30 // Code Version possible choices
31 //------------------------------ 31 //------------------------------
32 #define SIMULATION 1 32 #define SIMULATION 1
33 #define NOT_SIMULATION 2 33 #define NOT_SIMULATION 2
34 34
35 // RLC functions Version possible choices 35 // RCL functions Version possible choices
36 //------------------------------ 36 //------------------------------
37 #define POLL_FORCED 0 37 #define POLL_FORCED 0
38 #define RLC_SCENARIO 1 38 #define RLC_SCENARIO 1
39 #define MODEM_FLOW 2 39 #define MODEM_FLOW 2
40 40
41 // possible choices for UART trace output 41 // possible choices for UART trace output
42 //------------------------------ 42 //------------------------------
43 #if (CHIPSET != 15) 43 #define MODEM_UART 0
44 #define MODEM_UART 0 44 #define IRDA_UART 1
45 #define IRDA_UART 1 45 #if (CHIPSET == 12)
46 #if (CHIPSET == 12) 46 #define MODEM2_UART 2
47 #define MODEM2_UART 2
48 #endif
49 #else
50 // There is only one UART in Locosto
51 #define MODEM_UART 0
52 #endif 47 #endif
53 48
54 //============ 49 //============
55 // CODE CHOICE 50 // CODE CHOICE
56 //============ 51 //============
57 #if 0 52 #if 0
58 #if (OP_L1_STANDALONE==0) 53 #if (OP_L1_STANDALONE==0)
59 #define CODE_VERSION NOT_SIMULATION 54 #define CODE_VERSION NOT_SIMULATION
60 #else // OP_L1_STANDALONE 55 #else // OP_L1_STANDALONE
61 #ifdef WIN32 56 #ifdef WIN32
62 #define CODE_VERSION SIMULATION 57 #define CODE_VERSION SIMULATION
63 #else // WIN32 58 #else // WIN32
64 #define CODE_VERSION NOT_SIMULATION 59 #define CODE_VERSION NOT_SIMULATION
65 #endif // WIN32 60 #endif // WIN32
66 #endif // OP_L1_STANDALONE 61 #endif // OP_L1_STANDALONE
67 #endif // #if 0 62 #endif // #if 0
68 63
69 /* FreeCalypso */ 64 /* FreeCalypso */
92 //--------------------------------------------------------------------------------- 87 //---------------------------------------------------------------------------------
93 // Test with full simulation. 88 // Test with full simulation.
94 //--------------------------------------------------------------------------------- 89 //---------------------------------------------------------------------------------
95 #if (CODE_VERSION == SIMULATION) 90 #if (CODE_VERSION == SIMULATION)
96 91
97
98 #undef FF_L1_IT_DSP_USF
99 #define FF_L1_IT_DSP_USF 0
100 #undef FF_L1_IT_DSP_DTX
101 #if (AMR == 1)
102 #define FF_L1_IT_DSP_DTX 1 //it should be 1, sajal- temp made it 0 for build purpose
103 #else
104 #define FF_L1_IT_DSP_DTX 0
105 #endif
106
107 #define L1_DRP_IQ_SCALING 0
108
109 // Test Scenari... 92 // Test Scenari...
110 #define SCENARIO_FILE 1 // Test Scenario comes from input files. 93 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
111 #define SCENARIO_MEM 0 // Test Scenario comes from RAM. 94 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
112
113 // In Simulation AUDIO_DEBUG Should be 0
114 #define AUDIO_DEBUG 0
115 95
116 // Traces... 96 // Traces...
117 #undef TRACE_TYPE 97 #undef TRACE_TYPE
118 #define TRACE_TYPE 5 98 #define TRACE_TYPE 5
119 #define LOGFILE_TRACE 1 // trace in an output logfile 99 #define LOGFILE_TRACE 1 // trace in an output logfile
120
121 #define BURST_PARAM_LOG_ENABLE 0 // Burst Param Log Enable
122
123 #define FLOWCHART 0 // Message sequence/flow chart trace. 100 #define FLOWCHART 0 // Message sequence/flow chart trace.
124 #define NUCLEUS_TRACE 0 // Nucleus error trace 101 #define NUCLEUS_TRACE 0 // Nucleus error trace
125 #define EOTD_TRACE 1 // EOTD log trace 102 #define EOTD_TRACE 1 // EOTD log trace
126 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error 103 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
127 104
128 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible. 105 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
129 106
130 // Control algorithms... 107 // Control algorithms...
131 #define AFC_ALGO 1 // AFC algorithm. 108 #define AFC_ALGO 1 // AFC algorithm.
132 #if (L1_SAIC != 0)
133 #define TOA_ALGO 2 // TOA algorithm.
134 #else
135 #define TOA_ALGO 1 // TOA algorithm. 109 #define TOA_ALGO 1 // TOA algorithm.
136 #endif
137 #define AGC_ALGO 1 // AGC algorithm. 110 #define AGC_ALGO 1 // AGC algorithm.
138 #define TA_ALGO 0 // TA (Timing Advance) algorithm. 111 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
139 #undef VCXO_ALGO 112 #undef VCXO_ALGO
140 #define VCXO_ALGO 1 // VCXO algo 113 #define VCXO_ALGO 0 // VCXO algo
141 #undef DCO_ALGO 114 #undef DCO_ALGO
142 #define DCO_ALGO 0 // DCO algo (TIDE) 115 #define DCO_ALGO 0 // DCO algo (TIDE)
143 #undef ORDER2_TX_TEMP_CAL 116 #undef ORDER2_TX_TEMP_CAL
144 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection 117 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
145 118
152 #define AUDIO_TASK 1 // Enable the L1 audio features 125 #define AUDIO_TASK 1 // Enable the L1 audio features
153 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1) 126 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
154 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1) 127 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
155 128
156 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) 129 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
157 #define TTY_SYNC_MCU 0 // TTY WORKAROUND BUG03401 130 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401
158 #define TTY_SYNC_MCU_2 0 // 131 #define TTY_SYNC_MCU_2 1 //
159 #define L1_GTT_FIFO_TEST_ATOMIC 0 // 132 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
160 #define NEW_WKA_PATCH 0 133 #define NEW_WKA_PATCH 0
161 #define OPTIMISED 0 134 #define OPTIMISED 1
162 135
163 #define L1_RECOVERY 0 // L1 recovery 136 #define L1_RECOVERY 0 // L1 recovery
164 137
165 #undef L1_GPRS 138 #undef L1_GPRS
166 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities 139 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
180 #undef OP_RIV_AUDIO 153 #undef OP_RIV_AUDIO
181 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio 154 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
182 155
183 #undef OP_WCP 156 #undef OP_WCP
184 #define OP_WCP 0 // No WCP integration 157 #define OP_WCP 0 // No WCP integration
185
186 #undef L1_DRP
187 #define L1_DRP 0 // L1 supporting DRP interface
188
189 #undef DRP_MEM_SIMULATION
190 #define DRP_MEM_SIMULATION 0
191 //--------------------------------------------------------------------------------- 158 //---------------------------------------------------------------------------------
192 // Test with H/W platform. 159 // Test with H/W platform.
193 //--------------------------------------------------------------------------------- 160 //---------------------------------------------------------------------------------
194
195 #if (GSM_IDLE_RAM == 1)
196 #define GSM_IDLE_RAM_DEBUG 0
197 #endif
198
199 #define AFC_BYPASS_MODE 0
200 #define PWMEAS_IF_MODE_FORCE 0
201 // WA for OMAPS00099442 must be disabled in PC simulation
202 #undef L1_FF_WA_OMAPS00099442
203 #define L1_FF_WA_OMAPS00099442 0
204
205 #elif (CODE_VERSION == NOT_SIMULATION) 161 #elif (CODE_VERSION == NOT_SIMULATION)
206 162
207 #define L1_DRP_IQ_SCALING 1 163 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1)
208 // In Target AUDIO_DEBUG could be turned ON to debug any AUDIO ON/OFF issues
209 #define AUDIO_DEBUG 0
210
211 #if (GSM_IDLE_RAM == 1)
212 #if ((CHIPSET == 12) || (CHIPSET == 10))
213 #define GSM_IDLE_RAM_DEBUG 1
214 #else
215 #define GSM_IDLE_RAM_DEBUG 0
216 #endif
217 #else
218 #define GSM_IDLE_RAM_DEBUG 0
219 #endif
220
221 //FreeCalypso: L1_VPM commented out, as I suspect it's a LoCosto-ism
222 //#define L1_VPM 1
223
224 #if (OP_L1_STANDALONE == 1)
225 #if (CHIPSET == 15)
226 #if ((BOARD == 71) && (FLASH == 0))
227 // Not possible in I-SAMPLE only RAM configuration as there will
228 // not be enough memory space
229 #define BURST_PARAM_LOG_ENABLE 0
230 #else
231 #define BURST_PARAM_LOG_ENABLE 1
232 #endif
233 #else
234 #define BURST_PARAM_LOG_ENABLE 0
235 #endif
236 #else
237 #define BURST_PARAM_LOG_ENABLE 0
238 #endif
239
240 // Work around about Calypso RevA: the bus is floating (Cf PB01435) 164 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
241 // (corrected with Calypso ReV B and Calypso C035) 165 // (corrected with Calypso ReV B and Calypso C035)
242 #if (CHIPSET == 7) 166 #if (CHIPSET == 7)
243 #define W_A_CALYPSO_BUG_01435 1 167 #define W_A_CALYPSO_BUG_01435 1
244 #else 168 #else
245 #define W_A_CALYPSO_BUG_01435 0 169 #define W_A_CALYPSO_BUG_01435 0
246 #endif 170 #endif
247 171
248 #if (CHIPSET == 12) // Not needed for CHIPSET =15, as there is no extended page mode in Locosto
249 #define W_A_CALYPSO_PLUS_SPR_19599 1
250 #else
251 #define W_A_CALYPSO_PLUS_SPR_19599 0
252 #endif
253 172
254 // for AMR thresolds definition CQ22226 173 // for AMR thresolds definition CQ22226
255 #define W_A_AMR_THRESHOLDS 1 174 #define AMR_THRESHOLDS_WORKAROUND 1
256 #define W_A_PCTM_RX_AGC_GLOBAL_PARAMS 1 // For support of PCTM
257 175
258 #if (L1_GTT==1) 176 #if (L1_GTT==1)
259 #define TTY_SYNC_MCU 0 177 #define TTY_SYNC_MCU 1
260 #define TTY_SYNC_MCU_2 0 178 #define TTY_SYNC_MCU_2 1
261 #define L1_GTT_FIFO_TEST_ATOMIC 0 179 #define L1_GTT_FIFO_TEST_ATOMIC 0
262 #define NEW_WKA_PATCH 0 180 #define NEW_WKA_PATCH 0
263 #define OPTIMISED 0 181 #define OPTIMISED 1
264 #else 182 #else
265 #define TTY_SYNC_MCU_2 0 183 #define TTY_SYNC_MCU_2 0
266 #define L1_GTT_FIFO_TEST_ATOMIC 0 184 #define L1_GTT_FIFO_TEST_ATOMIC 0
267 #define TTY_SYNC_MCU 0 185 #define TTY_SYNC_MCU 0
268 #define NEW_WKA_PATCH 0 186 #define NEW_WKA_PATCH 0
269 #define OPTIMISED 0 187 #define OPTIMISED 0
270 188
271 #endif 189 #endif
272 190
273 /*
274 * FreeCalypso: these FF_L1_IT_DSP_USF and FF_L1_IT_DSP_DTX features (?)
275 * are new with the LoCosto L1 headers, i.e., not present in the Leonardo
276 * headers. I have no idea what they are, and I suspect they may likely
277 * be something that won't work on our Calypso platform, so I'm disabling
278 * them for now.
279 */
280
281 #undef FF_L1_IT_DSP_USF
282 #if 0 //(L1_GPRS == 1)
283 #define FF_L1_IT_DSP_USF 1
284 #else
285 #define FF_L1_IT_DSP_USF 0
286 #endif
287 #undef FF_L1_IT_DSP_DTX
288 #if 0 //(AMR == 1)
289 #define FF_L1_IT_DSP_DTX 1
290 #else
291 #define FF_L1_IT_DSP_DTX 0
292 #endif
293
294 // Traces... 191 // Traces...
295 #define NUCLEUS_TRACE 0 // Nucleus error trace 192 #define NUCLEUS_TRACE 0 // Nucleus error trace
296 #define FLOWCHART 0 // Message sequence/flow chart trace. 193 #define FLOWCHART 0 // Message sequence/flow chart trace.
297 #define LOGFILE_TRACE 0 // trace in an output logfile 194 #define LOGFILE_TRACE 0 // trace in an output logfile
298 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error 195 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
308 #endif 205 #endif
309 206
310 // Control algorithms... 207 // Control algorithms...
311 #define AFC_ALGO 1 // AFC algorithm. 208 #define AFC_ALGO 1 // AFC algorithm.
312 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!! 209 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
313 #if (L1_SAIC != 0)
314 #define TOA_ALGO 2 // TOA algorithm.
315 #else
316 #define TOA_ALGO 1 // TOA algorithm. 210 #define TOA_ALGO 1 // TOA algorithm.
317 #endif
318 #define AGC_ALGO 1 // AGC algorithm. 211 #define AGC_ALGO 1 // AGC algorithm.
319 #define TA_ALGO 1 // TA (Timing Advance) algorithm. 212 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
320 213
321 #define FACCH_TEST 0 // FACCH test enabled. 214 #define FACCH_TEST 0 // FACCH test enabled.
322 215
334 #define AUDIO_L1_STANDALONE 0 227 #define AUDIO_L1_STANDALONE 0
335 #endif 228 #endif
336 229
337 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) 230 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
338 231
339 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management 232 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
340 233
341 #define L1_RECOVERY 1 // L1 recovery 234 #define L1_RECOVERY 1 // L1 recovery
342 235
343 #if ((RF_FAM == 60) || (RF_FAM == 61))
344 #define L1_DRP 1 // L1 supporting DRP interface
345 #else
346 #define L1_DRP 0 // L1 supporting DRP interface
347 #endif
348 #define DRP_MEM_SIMULATION 0 // DRP memory simulation OFF by default
349 236
350 #if (L1_GPRS == 1) 237 #if (L1_GPRS == 1)
351 #define RLC_VERSION RLC_SCENARIO 238 #define RLC_VERSION RLC_SCENARIO
352 #if (RLC_VERSION == RLC_SCENARIO) 239 #if (RLC_VERSION == RLC_SCENARIO)
353 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO 240 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
369 256
370 #else 257 #else
371 #define DSP_BACKGROUND_TASKS 0 258 #define DSP_BACKGROUND_TASKS 0
372 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it 259 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
373 #endif 260 #endif
374 #define PWMEAS_IF_MODE_FORCE 1
375 // WA for OMAPS00099442 (OMAPS0010023 (N12.x), OMAPS000010022 (N5.x))
376 // The problem is: When NW is lost due to reception gap or cell border range,
377 // the MS will try to re-synchronize on the cell with the TPU timing aligned
378 // with the timing of the cell. So the FB will start within the 92 bits of the TPU window and
379 // will be missed. This issue is due to a limitation of the legacy FB demodulation algorithm
380 // WA is to re-initialize the TPU with an arbitrary timing value
381 #undef L1_FF_WA_OMAPS00099442
382 #define L1_FF_WA_OMAPS00099442 1
383
384 #endif 261 #endif
385 262
386 // Audio tasks selection 263 // Audio tasks selection
387 //----------------------- 264 //-----------------------
388 265
391 #define TONE 1 // Enable tone feature 268 #define TONE 1 // Enable tone feature
392 // Temporary modification for protocol stack compatibility - GSMLITE will be removed 269 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
393 #if (OP_L1_STANDALONE == 1) 270 #if (OP_L1_STANDALONE == 1)
394 #define GSMLITE 1 271 #define GSMLITE 1
395 #endif 272 #endif
396 #if (CODE_VERSION == SIMULATION)
397 #define L1_VOICE_MEMO 1
398 #endif
399 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE)) 273 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE))
400 #define MELODY_E1 1 // Enable melody format E1 feature 274 #define MELODY_E1 1 // Enable melody format E1 feature
401 275 #define VOICE_MEMO 1 // Enable voice memorization feature
402 #if(L1_VOICE_MEMO == 1) 276
403 #define VOICE_MEMO 1 // Enable voice memorization feature
404 #else
405 #define VOICE_MEMO 0
406 #endif
407 #define FIR 1 // Enable FIR feature 277 #define FIR 1 // Enable FIR feature
408 #if (DSP >= 33) 278 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
409 #define AUDIO_MODE 1 // Enable Audio mode feature 279 #define AUDIO_MODE 1 // Enable Audio mode feature
410 #else 280 #else
411 #define AUDIO_MODE 0 // Disable Audio mode feature 281 #define AUDIO_MODE 0 // Disable Audio mode feature
412 #endif 282 #endif
413 #else 283 #else
414 #define MELODY_E1 0 // Disable melody format E1 feature 284 #define MELODY_E1 0 // Disable melody format E1 feature
415 #if(L1_VOICE_MEMO == 1) 285 #define VOICE_MEMO 0 // Disable voice memorization feature
416 #define VOICE_MEMO 1 // Enable voice memorization feature
417 #else
418 #define VOICE_MEMO 0
419 #endif
420 #if (MELODY_E2) 286 #if (MELODY_E2)
421 #define FIR 1 // Enable FIR feature 287 #define FIR 1 // Enable FIR feature
422 #else 288 #else
423 #define FIR 0 // Disable FIR feature 289 #define FIR 0 // Disable FIR feature
424 #endif 290 #endif
291
425 #define AUDIO_MODE 0 // Disable Audio mode feature 292 #define AUDIO_MODE 0 // Disable Audio mode feature
426 #endif 293 #endif
427 294 // Define CPORT for ESample only
295 #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36)))
296 #define L1_CPORT 1 // Enable cport feature
297 #else
298 #define L1_CPORT 0 // Disable cport feature
299 #endif
428 300
429 #else 301 #else
430 #define KEYBEEP 0 // Enable keybeep feature 302 #define KEYBEEP 0 // Enable keybeep feature
431 #define TONE 0 // Enable tone feature 303 #define TONE 0 // Enable tone feature
432 #define MELODY_E1 0 // Enable melody format E1 feature 304 #define MELODY_E1 0 // Enable melody format E1 feature
433 #define VOICE_MEMO 0 // Enable voice memorization feature 305 #define VOICE_MEMO 0 // Enable voice memorization feature
306
434 #define FIR 0 // Enable FIR feature 307 #define FIR 0 // Enable FIR feature
435 #define AUDIO_MODE 0 // Enable Audio mode feature 308 #define AUDIO_MODE 0 // Enable Audio mode feature
436 #endif 309 #define L1_CPORT 0 // Enable cport feature
437 310 #endif
438 //FreeCalypso: LoCosto-ism below disabled
439 //#define L1_MIDI_BUFFER 1
440
441 /*
442 * L1_CPORT appears in the Leonardo L1 headers, and is enabled only for
443 * CHIPSET 12. The LoCosto version doesn't have it at all.
444 */
445 #define L1_CPORT 0
446 311
447 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2 312 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2
448 #if (OP_RIV_AUDIO == 1) 313 #if (OP_RIV_AUDIO == 1)
449 #define L1_AUDIO_DRIVER (L1_VOICE_MEMO_AMR | L1_EXT_AUDIO_MGT | L1_MP3) // Riviera audio driver (only Voice Memo AMR is available) 314 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
450 #endif 315 #endif
451 316
452 317
453 // Vocoder selections 318 // Vocoder selections
454 //------------------- 319 //-------------------
458 #define FR_EFR 3 // Full Rate + Enhanced Full Rate 323 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
459 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate 324 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
460 325
461 // Standard (frequency plan) selections 326 // Standard (frequency plan) selections
462 //------------------------------------- 327 //-------------------------------------
463 #if(L1_FF_MULTIBAND == 0) // std id is not used if multiband feature is enabled
464 328
465 #define GSM 1 // GSM900. 329 #define GSM 1 // GSM900.
466 #define GSM_E 2 // GSM900 Extended. 330 #define GSM_E 2 // GSM900 Extended.
467 #define PCS1900 3 // PCS1900. 331 #define PCS1900 3 // PCS1900.
468 #define DCS1800 4 // DCS1800. 332 #define DCS1800 4 // DCS1800.
469 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands) 333 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
470 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands) 334 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
471 #define GSM850 7 // GSM850 Band 335 #define GSM850 7 // GSM850 Band
472 #define DUAL_US 8 // PCS1900 + GSM850 336 #define DUAL_US 8 // PCS1900 + GSM850
473 337
474 #endif // L1_FF_MULTIBAND
475
476 /*------------------------------------*/ 338 /*------------------------------------*/
477 /* Power Management */ 339 /* Power Management */
478 /*------------------------------------*/ 340 /*------------------------------------*/
479 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1 341 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
480 342
481 /*------------------------------------*/ 343
482 /* BT Audio */
483 /*------------------------------------*/
484 #if ((L1_MP3 == 1) || (L1_AAC == 1))
485 #if (OP_L1_STANDALONE == 0)
486 #if((PSP_STANDALONE == 1) || (DRP_FW_BUILD == 1))
487 #define L1_BT_AUDIO 0
488 #else
489 #define L1_BT_AUDIO 1
490 #endif
491 #else
492 #define L1_BT_AUDIO 0
493 #endif
494 #endif
495 /*---------------------------------------------------------------------------*/ 344 /*---------------------------------------------------------------------------*/
496 /* DSP configurations */ 345 /* DSP configurations */
497 /* ------------------ */ 346 /* ------------------ */
498 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */ 347 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */
499 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */ 348 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */
550 /*-------------------------------*/ 399 /*-------------------------------*/
551 #if (MELODY_E2) 400 #if (MELODY_E2)
552 // In case of the melody E2 the DSP trace must be disable because the 401 // In case of the melody E2 the DSP trace must be disable because the
553 // melody instrument waves are overlayed with DSP trace buffer 402 // melody instrument waves are overlayed with DSP trace buffer
554 403
555 // DSP debug trace API buffer config 404 // DSP debug trace API buufer config
556 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 405 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
557 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 406 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
558 #else 407 #else
559 // DSP debug trace API buffer config 408 // DSP debug trace API buufer config
560 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 409 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
561 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 410 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
562 #endif 411 #endif
563 412
564 #elif (DSP == 30) // First GPRS. 413 #elif (DSP == 30) // First GPRS.
617 #define CLKMOD2 0x4116 // ...65 Mips pll free 466 #define CLKMOD2 0x4116 // ...65 Mips pll free
618 #define CLKSTART 0x29 // ...65 Mips 467 #define CLKSTART 0x29 // ...65 Mips
619 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 468 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
620 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 469 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
621 #define AEC 1 // AEC/NS not supported. 470 #define AEC 1 // AEC/NS not supported.
622 #define L1_NEW_AEC 1 471 #if (OP_RIV_AUDIO == 0)
623 472 #define L1_NEW_AEC 1
473 #else
474 // Available but not yet tuned with Riviera AUDIO
475 #define L1_NEW_AEC 0
476 #endif
624 #if ((L1_NEW_AEC) && (!AEC)) 477 #if ((L1_NEW_AEC) && (!AEC))
625 // First undef the flag to avoid warnings at compilation time 478 // First undef the flag to avoid warnings at compilation time
626 #undef AEC 479 #undef AEC
627 #define AEC 1 480 #define AEC 1
628 #endif 481 #endif
636 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 489 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
637 #define ULYSSE 0 490 #define ULYSSE 0
638 491
639 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 492 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
640 493
641 #if (CODE_VERSION == NOT_SIMULATION) 494 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
495
642 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 496 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
497
643 // management. 498 // management.
644 // DSP_IDLE3 is not supported in simulation 499
500 // DSP_IDLE3 is not supported in simulation
501
645 #else 502 #else
646 #define W_A_DSP_IDLE3 0 503 #define W_A_DSP_IDLE3 0
647 #endif 504 #endif
648 505
649 // DSP software work-around config 506 // DSP software work-around config
667 /*-------------------------------*/ 524 /*-------------------------------*/
668 #if (MELODY_E2) 525 #if (MELODY_E2)
669 // In case of the melody E2 the DSP trace must be disable because the 526 // In case of the melody E2 the DSP trace must be disable because the
670 // melody instrument waves are overlayed with DSP trace buffer 527 // melody instrument waves are overlayed with DSP trace buffer
671 528
672 // DSP debug trace API buffer config 529 // DSP debug trace API buufer config
673 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 530 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
674 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 531 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
675 532
676 // DSP debug trace type config 533 // DSP debug trace type config
677 // |<-------------- Features -------------->|<---------- Levels ----------->| 534 // |<-------------- Features -------------->|<---------- Levels ----------->|
681 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 538 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
682 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 539 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
683 // Currently not supported ! 540 // Currently not supported !
684 #endif 541 #endif
685 #else 542 #else
686 // DSP debug trace API buffer config 543 // DSP debug trace API buufer config
687 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 544 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
688 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 545 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
689 546
690 // DSP debug trace type config 547 // DSP debug trace type config
691 // |<-------------- Features -------------->|<---------- Levels ----------->| 548 // |<-------------- Features -------------->|<---------- Levels ----------->|
692 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 549 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
693 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. 550 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
694 551
695 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 552 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
696 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) 553 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
697 #endif 554 #endif
698 #endif 555 #endif
699 /* d_error_status */ 556 /* d_error_status */
700 /*-------------------------------*/ 557 /*-------------------------------*/
701 558
702 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 559 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
703 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 560 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
704 561
705 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 562 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
706 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 563 #define DSP_DEBUG_GSM_MASK 0x0000
707 #define DSP_DEBUG_GPRS_MASK 0x0f3d 564 #define DSP_DEBUG_GPRS_MASK 0x0f3d
708 #endif 565 #endif
709 566
710 #if DCO_ALGO 567 #if DCO_ALGO
711 // DCO type of scheduling 568 // DCO type of scheduling
717 #define CLKMOD2 0x4116 // ...65 Mips pll free 574 #define CLKMOD2 0x4116 // ...65 Mips pll free
718 #define CLKSTART 0x29 // ...65 Mips 575 #define CLKSTART 0x29 // ...65 Mips
719 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 576 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
720 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 577 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
721 #define AEC 1 // AEC/NS not supported. 578 #define AEC 1 // AEC/NS not supported.
722 #define L1_NEW_AEC 1 579 #if (OP_RIV_AUDIO == 0)
723 580 #define L1_NEW_AEC 1
581 #else
582 // Available but not yet tuned with Riviera AUDIO
583 #define L1_NEW_AEC 0
584 #endif
724 #if ((L1_NEW_AEC) && (!AEC)) 585 #if ((L1_NEW_AEC) && (!AEC))
725 // First undef the flag to avoid warnings at compilation time 586 // First undef the flag to avoid warnings at compilation time
726 #undef AEC 587 #undef AEC
727 #define AEC 1 588 #define AEC 1
728 #endif 589 #endif
735 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 596 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
736 #define ULYSSE 0 597 #define ULYSSE 0
737 598
738 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 599 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
739 600
740 #if (CODE_VERSION == NOT_SIMULATION) 601 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
741 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 602
742 // management. 603 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
743 // DSP_IDLE3 is not supported in simulation 604
605 // management.
606
607 // DSP_IDLE3 is not supported in simulation
608
744 #else 609 #else
745 #define W_A_DSP_IDLE3 0 610 #define W_A_DSP_IDLE3 0
746 #endif 611 #endif
747 612
748 // DSP software work-around config 613 // DSP software work-around config
765 /*-------------------------------*/ 630 /*-------------------------------*/
766 #if (MELODY_E2) 631 #if (MELODY_E2)
767 // In case of the melody E2 the DSP trace must be disable because the 632 // In case of the melody E2 the DSP trace must be disable because the
768 // melody instrument waves are overlayed with DSP trace buffer 633 // melody instrument waves are overlayed with DSP trace buffer
769 634
770 // DSP debug trace API buffer config 635 // DSP debug trace API buufer config
771 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 636 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
772 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 637 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
773 638
774 // DSP debug trace type config 639 // DSP debug trace type config
775 // |<-------------- Features -------------->|<---------- Levels ----------->| 640 // |<-------------- Features -------------->|<---------- Levels ----------->|
779 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 644 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
780 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 645 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
781 // Currently not supported ! 646 // Currently not supported !
782 #endif 647 #endif
783 #else 648 #else
784 // DSP debug trace API buffer config 649 // DSP debug trace API buufer config
785 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 650 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
786 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 651 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
787 652
788 // DSP debug trace type config 653 // DSP debug trace type config
789 // |<-------------- Features -------------->|<---------- Levels ----------->| 654 // |<-------------- Features -------------->|<---------- Levels ----------->|
790 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 655 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
791 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. 656 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
792 657
793 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 658 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
794 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) 659 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
795 #endif 660 #endif
796 661
797 // AMR trace 662 // AMR trace
798 #define C_AMR_TRACE_ID 55 663 #define C_AMR_TRACE_ID 55
799 664
802 /*-------------------------------*/ 667 /*-------------------------------*/
803 668
804 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 669 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
805 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 670 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
806 671
807 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 672 // masks to apply on d_error_status bit field
808 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 673 #define DSP_DEBUG_GSM_MASK 0x0000
809 #define DSP_DEBUG_GPRS_MASK 0x0f3d 674 #define DSP_DEBUG_GPRS_MASK 0x0f3d
810 #endif 675 #endif
811 676
812 #elif (DSP == 35) // ROM Code GPRS AMR. 677 #elif (DSP == 35) // ROM Code GPRS AMR.
813 #define CLKMOD1 0x4006 // ... 678 #define CLKMOD1 0x4006 // ...
814 #define CLKMOD2 0x4116 // ...65 Mips pll free 679 #define CLKMOD2 0x4116 // ...65 Mips pll free
815 #define CLKSTART 0x29 // ...65 Mips 680 #define CLKSTART 0x29 // ...65 Mips
816 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 681 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
817 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 682 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
818 #define AEC 1 // AEC/NS not supported. 683 #define AEC 1 // AEC/NS not supported.
819 #define L1_NEW_AEC 1 684 #if (OP_RIV_AUDIO == 0)
820 685 #define L1_NEW_AEC 1
686 #else
687 // Available but not yet tuned with Riviera AUDIO
688 #define L1_NEW_AEC 0
689 #endif
821 #if ((L1_NEW_AEC) && (!AEC)) 690 #if ((L1_NEW_AEC) && (!AEC))
822 // First undef the flag to avoid warnings at compilation time 691 // First undef the flag to avoid warnings at compilation time
823 #undef AEC 692 #undef AEC
824 #define AEC 1 693 #define AEC 1
825 #endif 694 #endif
826 #define MAP 3 695 #define MAP 3
827 696
828 #define FF_L1_TCH_VOCODER_CONTROL 1 697 #define FF_L1_TCH_VOCODER_CONTROL 1
829 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 698 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
830 699
831 #define DSP_START 0x7000 700 #define DSP_START 0x7000
832 701
833 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer 702 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
834 703
835 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 704 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
836 #define ULYSSE 0 705 #define ULYSSE 0
837 706
838 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 707 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
839 708
840 #if (CODE_VERSION == NOT_SIMULATION) 709 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
841 #if (CHIPSET != 12) 710
842 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 711 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
843 // management. 712
844 // DSP_IDLE3 is not supported in simulation 713 // management.
845 #else 714
846 #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep 715 // DSP_IDLE3 is not supported in simulation
847 // management. 716
848 // DSP_IDLE3 is not supported in simulation 717 #else
849 #endif // CHIPSET 12 718 #define W_A_DSP_IDLE3 0
850 #else 719 #endif
851 #define W_A_DSP_IDLE3 0
852 #endif
853
854 #define W_A_DSP_PR20037 1
855 720
856 // DSP software work-around config 721 // DSP software work-around config
857 // bit0 - Work-around to support CRTG. 722 // bit0 - Work-around to support CRTG.
858 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 723 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
859 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 724 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
873 /*-------------------------------*/ 738 /*-------------------------------*/
874 #if (MELODY_E2) 739 #if (MELODY_E2)
875 // In case of the melody E2 the DSP trace must be disable because the 740 // In case of the melody E2 the DSP trace must be disable because the
876 // melody instrument waves are overlayed with DSP trace buffer 741 // melody instrument waves are overlayed with DSP trace buffer
877 742
878 // DSP debug trace API buffer config 743 // DSP debug trace API buufer config
879 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 744 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
880 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. 745 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
881 746
882 // DSP debug trace type config 747 // DSP debug trace type config
883 // |<-------------- Features -------------->|<---------- Levels ----------->| 748 // |<-------------- Features -------------->|<---------- Levels ----------->|
887 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 752 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
888 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 753 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
889 // Currently not supported ! 754 // Currently not supported !
890 #endif 755 #endif
891 #else 756 #else
892 // DSP debug trace API buffer config 757 // DSP debug trace API buufer config
893 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 758 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
894 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 759 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
895 760
896 // DSP debug trace type config 761 // DSP debug trace type config
897 // |<-------------- Features -------------->|<---------- Levels ----------->| 762 // |<-------------- Features -------------->|<---------- Levels ----------->|
898 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 763 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
899 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst. 764 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
900 765
901 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 766 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
902 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) 767 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
903 #endif 768 #endif
904 769
905 // AMR trace 770 // AMR trace
906 #define C_AMR_TRACE_ID 55 771 #define C_AMR_TRACE_ID 55
907 772
911 776
912 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 777 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
913 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 778 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
914 779
915 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 780 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
916 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 781 #define DSP_DEBUG_GSM_MASK 0x08BD
917 #define DSP_DEBUG_GPRS_MASK 0x0f3d 782 #define DSP_DEBUG_GPRS_MASK 0x0f3d
918 #endif 783 #endif
919 #elif (DSP >= 36) // ROM Code GPRS AMR. 784 #elif (DSP == 36) // ROM Code GPRS AMR.
920
921 #if ((L1_PCM_EXTRACTION) && (SPEECH_RECO))
922 #error "PCM extraction and Speech recognition not supported simultaneously"
923 #endif
924
925 #define CLKMOD1 0x4006 // ... 785 #define CLKMOD1 0x4006 // ...
926 #define CLKMOD2 0x4116 // ...65 Mips pll free 786 #define CLKMOD2 0x4116 // ...65 Mips pll free
927 #define CLKSTART 0x29 // ...65 Mips 787 #define CLKSTART 0x29 // ...65 Mips
928 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips 788 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
929 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). 789 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
930
931 #if 0
932 /* what we got with LoCosto L1 headers */
933 #define AEC 0 // AEC/NS not supported.
934 #define L1_NEW_AEC 0
935 #else
936 /* what we are used to from the Leonardo version */
937 #define AEC 1 // AEC/NS not supported. 790 #define AEC 1 // AEC/NS not supported.
938 #if (OP_RIV_AUDIO == 0) 791 #if (OP_RIV_AUDIO == 0)
939 #define L1_NEW_AEC 1 792 #define L1_NEW_AEC 1
940 #else 793 #else
941 // Available but not yet tuned with Riviera AUDIO 794 // Available but not yet tuned with Riviera AUDIO
942 #define L1_NEW_AEC 0 795 #define L1_NEW_AEC 0
943 #endif 796 #endif
944 #endif
945
946 #if ((L1_NEW_AEC) && (!AEC)) 797 #if ((L1_NEW_AEC) && (!AEC))
947 // First undef the flag to avoid warnings at compilation time 798 // First undef the flag to avoid warnings at compilation time
948 #undef AEC 799 #undef AEC
949 #define AEC 1 800 #define AEC 1
950 #endif 801 #endif
951 #define MAP 3 802 #define MAP 3
952 #undef L1_AMR_NSYNC 803 #undef L1_AMR_NSYNC
953 #define L1_AMR_NSYNC 1 804 #define L1_AMR_NSYNC 1
954 #define FF_L1_TCH_VOCODER_CONTROL 1 805 #define FF_L1_TCH_VOCODER_CONTROL 1
955 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 806 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
956 807
957 #define DSP_START 0x7000 808 #define DSP_START 0x7000
958 809
959 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer 810 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
960 811
961 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH 812 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
962 #define ULYSSE 0 813 #define ULYSSE 0
963 814
964 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. 815 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
965 816
966 #if (CODE_VERSION == NOT_SIMULATION) 817 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
967 #if ((CHIPSET != 12) && (CHIPSET != 15)) 818
968 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep 819 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
969 // management. 820
970 // DSP_IDLE3 is not supported in simulation 821 // management.
971 #else // CHIPSET 12 822
972 #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep 823 // DSP_IDLE3 is not supported in simulation
973 // management. 824
974 // DSP_IDLE3 is not supported in simulation 825 #else
975 #endif // CHIPSET 12
976 #else // CODE_VERSION
977 #define W_A_DSP_IDLE3 0 826 #define W_A_DSP_IDLE3 0
978 #endif 827 #endif
979
980 #define W_A_DSP_PR20037 1
981 828
982 // DSP software work-around config 829 // DSP software work-around config
983 // bit0 - Work-around to support CRTG. 830 // bit0 - Work-around to support CRTG.
984 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 831 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
985 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 832 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
990 #elif (ANALOG == 2) // IOTA 837 #elif (ANALOG == 2) // IOTA
991 #define C_DSP_SW_WORK_AROUND 0x000E 838 #define C_DSP_SW_WORK_AROUND 0x000E
992 839
993 #elif (ANALOG == 3) // SYREN 840 #elif (ANALOG == 3) // SYREN
994 #define C_DSP_SW_WORK_AROUND 0x000E 841 #define C_DSP_SW_WORK_AROUND 0x000E
995 842 #endif
996 #elif (ANALOG == 11) // TRITON 843
997 #define C_DSP_SW_WORK_AROUND 0x000E 844 // This workaround should be enabled only for H2-sample on full build config
998 845 #if (OP_L1_STANDALONE==1)
846 #define RAZ_VULSWITCH_REGAUDIO 0
999 #endif 847 #endif
1000 848
1001 /* DSP debug trace configuration */ 849 /* DSP debug trace configuration */
1002 /*-------------------------------*/ 850 /*-------------------------------*/
1003 // Note: 851 #if (MELODY_E2)
1004 // In case of melody E2, MP3, AAC or Dyn Dwnld ACTIVITY the DSP trace is automatically disabled 852 // In case of the melody E2 the DSP trace must be disable because the
1005 // because the melody instrument waves are overlayed with DSP trace buffer (supported since patch 7c20) 853 // melody instrument waves are overlayed with DSP trace buffer
1006 854
1007 // DSP debug trace API buffer config 855 // DSP debug trace API buufer config
1008 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. 856 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1009 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. 857 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
1010 858
1011 // DSP debug trace type config 859 // DSP debug trace type config
1012 // |<-------------- Features -------------->|<---------- Levels ----------->| 860 // |<-------------- Features -------------->|<---------- Levels ----------->|
1013 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] 861 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
1014 862 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
1015 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)// C_DEBUG_TRACE_TYPE 0x0012 changed from 0x0054 for DSP load reduce
1016 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = KERNEL; Features = Timer, Burst, Buffer Header.
1017 #else
1018 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = KERNEL; Features = Timer, Burst, Buffer Header.
1019 #endif
1020
1021 863
1022 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 864 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
1023 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability 865 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1024 // Currently not supported ! 866 // Currently not supported !
1025 #endif 867 #endif
868 #else
869 // DSP debug trace API buufer config
870 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
871 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
872
873 // DSP debug trace type config
874 // |<-------------- Features -------------->|<---------- Levels ----------->|
875 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
876 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
877
878 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
879 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
880 #endif
1026 881
1027 // AMR trace 882 // AMR trace
1028 #define C_AMR_TRACE_ID 55 883 #define C_AMR_TRACE_ID 55
1029 884
1030 885 #endif
1031 /* d_error_status */ 886 /* d_error_status */
1032 /*-------------------------------*/ 887 /*-------------------------------*/
1033 888
1034 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) 889 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
1035 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) 890 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1036 891
1037 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 892 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1038 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852 893 #define DSP_DEBUG_GSM_MASK 0x08BD
1039 #define DSP_DEBUG_GPRS_MASK 0x0f3d 894 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1040 #endif 895 #endif
1041 #endif // DSP 896 #endif // DSP
1042 897
1043 /*------------------------------------*/ 898 /*------------------------------------*/
1088 #define L1_AMR_NSYNC 0 943 #define L1_AMR_NSYNC 0
1089 #endif 944 #endif
1090 945
1091 #ifndef FF_L1_TCH_VOCODER_CONTROL 946 #ifndef FF_L1_TCH_VOCODER_CONTROL
1092 #define FF_L1_TCH_VOCODER_CONTROL 0 947 #define FF_L1_TCH_VOCODER_CONTROL 0
1093 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0 948 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
1094 #define W_A_DSP_PR20037 0 949 #endif
1095 #endif
1096
1097 950
1098 /*------------------------------------*/ 951 /*------------------------------------*/
1099 /* Download */ 952 /* Download */
1100 /*------------------------------------*/ 953 /*------------------------------------*/
1101 954
1123 #define PATCH_DSP_DWNLD 3 976 #define PATCH_DSP_DWNLD 3
1124 977
1125 // MAC-S status reporting to Layer 1 978 // MAC-S status reporting to Layer 1
1126 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1 979 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
1127 980
1128 /* 981
1129 * Possible choice for dll_dcch_downlink interface (with FN or without FN) 982 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
1130 * 0=without, 1=with FN parameter 983 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
1131 *
1132 * FreeCalypso note: the Leonardo version had this setting set to 1, i.e.,
1133 * 3 arguments to dll_dcch_downlink(). We don't have any source or even
1134 * header files for the Leonardo version of DL, but disassembly shows
1135 * that dll_dcch_downlink() does expect the FN parameter. The source for
1136 * DL from LoCosto also has a SEND_FN_TO_L2_IN_DCCH configurable setting,
1137 * and it is set to 1 in the dl.h local header. But here is the kicker:
1138 * the LoCosto version of this l1_confg.h header has the setting set to 0!
1139 *
1140 * I couldn't believe my eyes, so I disassembled the binary objects present
1141 * in the copy of the LoCosto source from scottn.us: yes, indeed that
1142 * code version contains an outright bug in that L1 does not pass the
1143 * 3rd argument (in ARM register r2), but DL expects it to be there.
1144 * (Thus DL is getting whatever "garbage" happens to be in r2 as the FN
1145 * parameter. I did not take the time to investigate what the downstream
1146 * effects are.)
1147 *
1148 * For FreeCalypso I'm setting SEND_FN_TO_L2_IN_DCCH to 1, both here
1149 * in L1 and in DL, where it was already set.
1150 */
1151 #define SEND_FN_TO_L2_IN_DCCH 1
1152
1153 /*
1154 * FreeCalypso change: I'm disabling L1_CHECK_COMPATIBLE (a new "feature"
1155 * added with LoCosto version of L1, not present in the Leonardo version)
1156 * because l1_async.c fails to compile with it enabled. Examination of
1157 * the code reveals that this "compatibility check" involves things
1158 * which we won't be enabling any time soon, if ever.
1159 */
1160 #define L1_CHECK_COMPATIBLE 0 //Check L1A message compatiblity
1161 984
1162 //--------------------------------------------------------------------------------- 985 //---------------------------------------------------------------------------------
1163 986
987 // Neighbor Cell RXLEV indication
988 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
989 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
990 #else
991 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
992 #endif
993
1164 #endif /* __L1_CONFG_H__ */ 994 #endif /* __L1_CONFG_H__ */