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comparison src/cs/layer1/tpu_drivers/source0/tpudrv35.h @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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1 /****************** Revision Controle System Header ***********************
2 * GSM Layer 1 software
3 * Copyright (c) Texas Instruments 2001
4 *
5 * Filename tpudrv35.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ****************** Revision Controle System Header ***********************/
9
10 //TRF2253 definitions
11 #define WordAdd0000 0x000000 //Main Configuration
12 #define AutoPDB 0x000080 //Auto Power Down - Uses PWDNB pin
13 #define AuxSel 0x030000 //Auxiliary output pin use = LOCK Detect
14 #define WordAdd0011 0x000003 //RF1 N Divider
15 #define WordAdd0100 0x000004 //RF2 N Divider
16 #define WordAdd0101 0x000005 //IF N Divider
17 #define RFPWR 0x000020 //RF LO high power
18 #define XPDM 0x000100 //Reference amplifier ON when PWDNB pin = 0
19
20 //TRF6053 definitions
21 #define Mode0 0x000000
22 #define Mode1 0x000001
23 #define Mode2 0x000003
24 #define Mode3 0x000005
25 #define Mode4 0x000007
26 #define LNAMixPwrOn 0x000080 //Mode0
27 #define VCODiv2PwrOn 0x000040 //Mode0
28 #define RXBBIFStgPwrOn 0x000020 //Mode0
29 #define OFFStrCalOn 0x000010 //Mode0
30 #define VCORDivPwrOn 0x000008 //Mode0
31 #define MixLOBuffPwrOn 0x000004 //Mode0
32 #define TXStagesPwrOn 0x000002 //Mode0
33
34 #define BandHigh 0x000008 //Mode1
35
36 #define LNAGainLow 0x000010 //Mode2
37 #define ChgPPLBNeg 0x000010 //Mode2
38 #define LowBIF610 0x000020 //Mode2
39 #define PreCCLBDis 0x000008 //Mode2
40
41 #define ChgPPHBNeg 0x000010 //Mode3
42 #define PreCCHBDis 0x000008 //Mode3
43 #define HighBIF412 0x000020 //Mode3
44 #define HighBIF25 0x000040 //Mode3
45 #define HighBIF410 0x000060 //Mode3
46
47 #define FreqDetDis 0x000400 //Mode4
48 #define IFVCOExternal 0x000200 //Mode4
49 #define IFPLLBuffDis 0x000100 //Mode4
50 #define LBandLNAExt 0x000080 //Mode4
51 #define HBandLNAExt 0x000040 //Mode4
52 #define Div2ToRXStgs 0x000020 //Mode4
53 #define DivRToTXStgs 0x000010 //Mode4
54
55 /*------------------------------------------*/
56 /* Download delay values */
57 /*------------------------------------------*/
58 #define TRF6053_DOWNLOAD_TIME 15
59 #define SYNTH_DOWNLOAD_TIME 20
60
61 //--------------------------------------------
62 // internal tpu timing
63 //--------------------------------------------
64
65 #define DLT_1 1 // 1 tpu instruction = 1 qbit
66 #define DLT_2 2
67 #define DLT_3 3
68 #define DLT_4 4
69
70 #define DLT_1B 4 // 3*move + 1*byte (download)
71 #define DLT_2B 6 // 4*move + 2*byte
72 #define DLT_3B 8 // 5*move + 3*byte
73
74 #define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1
75 #define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1
76 #define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization
77
78 /*------------------------------------------*/
79 /* Download delay values */
80 /*------------------------------------------*/
81 // 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit
82
83 #define T TPU_CLOCK_RANGE // TODO: should be a define from L1.
84
85 // time below are offset to when BDLENA goes low
86 #define TRF_R13 ( 5 - DLT_1B ) // disable rx path, fe, lna_gain
87 #define TRF_R11 ( 0 - DLT_1B) // disable BDLON & BDLENA
88 #define TRF_R10 ( - 5 - DLT_1B) // disable TRF6053
89
90 // burst data comes here
91 // time below are offset to when BDLENA goes high
92 #define TRF_R9 (PROVISION_TIME - 0 - DLT_1B) // enable BDLENA, disable BDLCAL
93 #define TRF_R8 (PROVISION_TIME - 11 - DLT_1B) // set rx path + power on RX front end, DC cal. off
94 #define TRF_R7 (PROVISION_TIME - 65 - DLT_1B) // enable BDLCAL
95 #define TRF_R6 (PROVISION_TIME - 72 - DLT_1B) // enable BDLON
96 #define TRF_R5 (PROVISION_TIME - 76 - DLT_1B) // power on receiver, start DC cal.
97 #define TRF_R4 (PROVISION_TIME - 80 - DLT_2B) // set RX gain & band.
98 // ADC read, uses min 11 qbit due to 5 wait
99 #define TRF_R3 (PROVISION_TIME - 196 - DLT_1B) // power up TRF2253
100 #define TRF_R1 (PROVISION_TIME - 205 - DLT_3B) // set RF PLL N counter = r1 and IF PLL N counter in TRF2253 = r2
101
102 // time below are offset to when BULENA goes low
103 #define TRF_T14 ( 34 - DLT_2) // disable PA_ON, , BULON, fe, rx path & lna
104 #define TRF_T13 ( 29 - DLT_1B) // disable TRF6053
105 #define TRF_T12_1 ( 21 - DLT_1B) // disable fe_sw
106 //#define TRF_T12 ( 18 - DLT_1 ) // disable TSPACT01
107 #define TRF_T11 ( 0 - DLT_1B) // disable BULENA
108 #define TRF_T10_1 (- 40 - DLT_1B) // ADC read
109 // burst data comes here
110 // time below are offset to when BULENA goes high
111 #define TRF_T10_0 (+ 27 - DLT_1B) //enable PA_ON
112 #define TRF_T10 (+ 18 - DLT_1B) // set fe
113 #define TRF_T9 (- 0 - DLT_1B) // enable BULENA
114 #define TRF_T8_1 (- 100 - DLT_1B) // set TX_PCS_EN as required
115 #define TRF_T8 (- 108 - DLT_2B) // power on transceiver
116 #define TRF_T7 (- 115 - DLT_1B) // disable BULCAL
117 #define TRF_T6 (- 230 - DLT_1B) // power up TRF2253
118 #define TRF_T5 (- 233 - DLT_2B) // set TX band in TRF6053
119 #define TRF_T3 (- 249 - DLT_3B) // set RF PLL N counter = t3 and IF PLL N counter in TRF2253 = t4
120 #define TRF_T2 (- 260 - DLT_1B) // enable BULCAL
121 #define TRF_T1 (- 278 - DLT_1B) // enable BULON
122
123 #if ((BOARD == 34)||(BOARD == 35))
124
125 #define PA_ON 0x01 // act0
126 #define DCS_RX_EN 0x02 // act1
127 #define PCS_RX_EN 0x04 // act2
128 #define PCS_TX_EN 0x08 // act3
129 #define LNA_GAIN 0x10 // act4
130 #define TX_SW_1 0x20 // act5
131 #define TX_SW_2 0x40 // act6
132 #define TX_SW_3 0x80 // act7
133 #define TX_SW_OFF (TX_SW_1 | TX_SW_2 | TX_SW_3)
134
135 #define ACT_OFF TX_SW_OFF
136
137 #define RX_PATH_GSM ( TX_SW_1 | TX_SW_2 | TX_SW_3)
138 #define RX_PATH_DCS (DCS_RX_EN | TX_SW_1 | TX_SW_2 | TX_SW_3)
139 #define RX_PATH_PCS (PCS_RX_EN | TX_SW_1 | TX_SW_3)
140
141 #define TX_PATH_GSM ( TX_SW_1 | TX_SW_2 )
142 #define TX_PATH_DCS ( TX_SW_2 | TX_SW_3)
143 #define TX_PATH_PCS (DCS_RX_EN | TX_SW_2 | TX_SW_3)
144
145 #define TC1_DEVICE_ABB TC1_DEVICE0
146 #define TC1_DEVICE_RF TC1_DEVICE1
147 #define TC1_DEVICE_PLL TC1_DEVICE2
148 #define TC1_DEVICE_DATA_OUT TC1_DEVICE3 //todo: read data from rf and do stuff
149 #endif
150
151 typedef struct
152 {
153 UWORD16 data[6];
154 UWORD16 enable;
155 UWORD16 index;
156 UWORD16 write_index;
157 }
158 T_PLL_TUNING;
159
160 extern T_PLL_TUNING pll_tuning;
161
162 #ifdef TPUDRV35_C
163 // Function prototypes
164 SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq);
165
166 #endif