FreeCalypso > hg > ffs-editor
comparison src/cs/layer1/audio_include/l1audio_const.h @ 0:92470e5d0b9e
src: partial import from FC Selenite
| author | Mychaela Falconia <falcon@freecalypso.org> |
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| date | Fri, 15 May 2020 01:28:16 +0000 |
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| -1:000000000000 | 0:92470e5d0b9e |
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| 1 /************* Revision Controle System Header ************* | |
| 2 * GSM Layer 1 software | |
| 3 * L1AUDIO_CONST.H | |
| 4 * | |
| 5 * Filename l1audio_const.h | |
| 6 * Copyright 2003 (C) Texas Instruments | |
| 7 * | |
| 8 ************* Revision Controle System Header *************/ | |
| 9 | |
| 10 #if (AUDIO_TASK == 1) | |
| 11 | |
| 12 //---------------------------------------- | |
| 13 // LAYER 1 Synchronous audio process name. | |
| 14 //---------------------------------------- | |
| 15 | |
| 16 #define NBR_AUDIO_MANAGER 19 // Number of L1S audio managers | |
| 17 | |
| 18 #define L1S_KEYBEEP_STATE 0 // l1s_keybeep_manager() | |
| 19 #define L1S_TONE_STATE 1 // l1s_tone_manager() | |
| 20 #define L1S_MELODY0_STATE 2 // l1s_melody0_manager() | |
| 21 #define L1S_MELODY1_STATE 3 // l1s_melody1_manager() | |
| 22 #define L1S_VM_PLAY_STATE 4 // l1s_vm_play_manager() | |
| 23 #define L1S_VM_RECORD_STATE 5 // l1s_vm_record_manager() | |
| 24 #define L1S_TONE_UL_STATE 6 // l1s_tone_ul_manager() | |
| 25 #define L1S_SR_ENROLL_STATE 7 // l1s_sr_enroll_manager() | |
| 26 #define L1S_SR_UPDATE_STATE 8 // l1s_sr_update_manager() | |
| 27 #define L1S_SR_RECO_STATE 9 // l1s_sr_reco_manager() | |
| 28 #define L1S_SR_PROCESSING_STATE 10 // l1s_sr_processing_manager() | |
| 29 #define L1S_SR_SPEECH_STATE 11 // l1s_sr_speech_manager() | |
| 30 #define L1S_AEC_STATE 12 // l1s_aec_manager() | |
| 31 #define L1S_AUDIO_MODE_STATE 13 // l1s_audio_mode_manager() | |
| 32 #define L1S_MELODY0_E2_STATE 14 // l1s_melody0_e2_manager() | |
| 33 #define L1S_MELODY1_E2_STATE 15 // l1s_melody1_e2_manager() | |
| 34 #define L1S_VM_AMR_PLAY_STATE 16 // l1s_vm_amr_play_manager() | |
| 35 #define L1S_VM_AMR_RECORD_STATE 17 // l1s_vm_amr_record_manager() | |
| 36 #define L1S_CPORT_STATE 18 // l1s_cport_manager() | |
| 37 | |
| 38 //---------------------------------------- | |
| 39 // MCU<->DSP communication bit field. | |
| 40 //---------------------------------------- | |
| 41 | |
| 42 // bit in d_tch_mode for audio features | |
| 43 #define B_VOICE_MEMO_DTX (TRUE_L << 5) | |
| 44 #if (DSP == 34) || (DSP == 35) || (DSP == 36) | |
| 45 #define B_VM_VOCODER_SELECT (TRUE_L << 6) | |
| 46 #endif | |
| 47 | |
| 48 // bits in d_toneskb_status | |
| 49 #define B_TONE (TRUE_L << 0) // Indicate if the DSP tone task is running | |
| 50 #define B_KEYBEEP (TRUE_L << 1) // Indicate if the DSP Keybeep task is running | |
| 51 #define B_VM_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech task is running | |
| 52 #define B_VM_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing task is running | |
| 53 #define B_VM_AMR_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech amr task is running | |
| 54 #define B_VM_AMR_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing amr task is running | |
| 55 #define B_SR_ENROLL_TASK (TRUE_L << 4) // Indicate if the DSP enroll task is running | |
| 56 #define B_SR_UPDATE_TASK (TRUE_L << 5) // Indicate if the DSP update task is running | |
| 57 #define B_SR_RECO_TASK (TRUE_L << 6) // Indicate if the DSP reco task is running | |
| 58 #define B_SR_PROCESSING_TASK (TRUE_L << 7) // Indicate if the DSP processing task is running | |
| 59 #define B_SR_ALIGNMENT_TASK (TRUE_L << 8) // Indicate if the DSP alignment task is running | |
| 60 #define B_IT_COM_REQ (TRUE_L << 9) // Indicate that the DSP requests an IT com for the next TDMA | |
| 61 | |
| 62 // bits in d_toneskb_init | |
| 63 #define B_VM_RECORD_START (TRUE_L << 2) // Start the DSP voice memo recording task | |
| 64 #define B_VM_RECORD_STOP (TRUE_L << 3) // Stop the DSP voice memo recording task | |
| 65 #define B_VM_PLAY_START (TRUE_L << 4) // Start the DSP voice memo playing task | |
| 66 #define B_VM_PLAY_STOP (TRUE_L << 5) // Stop the DSP voice memo playing task | |
| 67 #define B_VM_TONE_UL (TRUE_L << 6) // Generate the tone on the UL path | |
| 68 #define B_VM_AMR_RECORD_START (TRUE_L << 2)// Start the DSP voice memo amr recording task | |
| 69 #define B_VM_AMR_RECORD_STOP (TRUE_L << 3)// Stop the DSP voice memo amr recording task | |
| 70 #define B_VM_AMR_PLAY_START (TRUE_L << 4)// Start the DSP voice memo amr playing task | |
| 71 #define B_VM_AMR_PLAY_STOP (TRUE_L << 5)// Stop the DSP voice memo amr playing task | |
| 72 #define B_SR_ENROLL (TRUE_L << 7) // Start the DSP speech reco enroll task | |
| 73 #define B_SR_UPDATE (TRUE_L << 8) // Start the DSP speech reco update task | |
| 74 #define B_SR_RECO (TRUE_L << 9) // Start the DSP speech reco task | |
| 75 #define B_SR_PROCESSING (TRUE_L << 10) // Start the DSP speech reco processing task | |
| 76 #define B_SR_STOP (TRUE_L << 11) // Stop the current DSP speech reco task | |
| 77 | |
| 78 #define B_MELO (TRUE_L << 13) // Start the DSP melody module if it's not started | |
| 79 #if (L1_CPORT == 1) | |
| 80 //---------------------------------------- | |
| 81 // C_PORT constant. | |
| 82 //---------------------------------------- | |
| 83 | |
| 84 #define CPORT_READ_FLAG_OFFSET 11 // offset in configuration field of the "read register" bit | |
| 85 #define CPORT_REG_NB_OFFSET 12 // offset in configuration field of the register number | |
| 86 #define CPORT_READ_MASK 0xF800 // mask to get the read flag and the read reg id in the d_cport_status field | |
| 87 | |
| 88 // write register defines | |
| 89 #define CPORT_W_NONE 0 // do not write anything | |
| 90 #define CPORT_W_CTRL 1 // write CTRL, set bit 0 of configuration to 1 | |
| 91 #define CPORT_W_CPCFR1 1 << 1 // write CPCFR1, set bit 1 of configuration to 1 | |
| 92 #define CPORT_W_CPCFR2 1 << 2 // write CPCFR2, set bit 2 of configuration to 1 | |
| 93 #define CPORT_W_CPCFR3 1 << 3 // write CPCFR3, set bit 3 of configuration to 1 | |
| 94 #define CPORT_W_CPCFR4 1 << 4 // write CPCFR4, set bit 4 of configuration to 1 | |
| 95 #define CPORT_W_CPTCTL 1 << 5 // write CPTCTL, set bit 5 of configuration to 1 | |
| 96 #define CPORT_W_CPTTADDR 1 << 6 // write CPTTADDR, set bit 6 of configuration to 1 | |
| 97 #define CPORT_W_CPTDAT 1 << 7 // write CPTDAT, set bit 7 of configuration to 1 | |
| 98 #define CPORT_W_CPTVS 1 << 8 // write CPTVS, set bit 8 of configuration to 1 | |
| 99 | |
| 100 // read register defines | |
| 101 #define CPORT_R_NONE 0 // do not read anything | |
| 102 // for each of the following defines, set read flag (bit 11) to 1 and set reg_nb (bits 12..15) | |
| 103 #define CPORT_R_CTRL (0 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 104 #define CPORT_R_CPCFR1 (1 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 105 #define CPORT_R_CPCFR2 (2 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 106 #define CPORT_R_CPCFR3 (3 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 107 #define CPORT_R_CPCFR4 (4 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 108 #define CPORT_R_CPTCTL (5 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 109 #define CPORT_R_CPTTADDR (6 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 110 #define CPORT_R_CPTDAT (7 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 111 #define CPORT_R_CPTVS (8 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 112 #define CPORT_R_STATUS (9 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
| 113 | |
| 114 #endif | |
| 115 | |
| 116 | |
| 117 #if (MELODY_E1) | |
| 118 //---------------------------------------- | |
| 119 // Melody constant. | |
| 120 //---------------------------------------- | |
| 121 | |
| 122 // Word to indicate that the oscillator must be stopped ASAP | |
| 123 #define SC_END_OSCILLATOR_MASK 0xfffe | |
| 124 | |
| 125 // Description of the ml_ocscil_x field (x= 0...SC_NUMBER_OSCILLATOR) | |
| 126 #define SC_MELO_OSCILLATOR_USED_MASK 0xff00 | |
| 127 #define SC_MELO_OSCILLATOR_USED_SHIFT SC_NUMBER_OSCILLATOR | |
| 128 | |
| 129 // Description of the ml_time_offset field | |
| 130 #define SC_MELO_TIME_OFFSET_MASK 0x00ff | |
| 131 #define SC_MELO_TIME_OFFSET_SHIFT 0 | |
| 132 | |
| 133 // Description of the ml_load1 bit | |
| 134 #define SC_MELO_LOAD1_MASK 0x0010 | |
| 135 #define SC_MELO_LOAD1_SHIFT 4 | |
| 136 | |
| 137 // Description of the ml_load2 bit | |
| 138 #define SC_MELO_LOAD2_MASK 0x0020 | |
| 139 #define SC_MELO_LOAD2_SHIFT 5 | |
| 140 | |
| 141 // Description of the ml_synchro bit | |
| 142 #define SC_MELO_SYNCHRO_MASK 0x0001 | |
| 143 #define SC_MELO_SYNCHRO_SHIFT 0 | |
| 144 | |
| 145 // Description of the ml_length field | |
| 146 #define SC_MELO_LENGTH_MASK 0xffc0 | |
| 147 #define SC_MELO_LENGTH_SHIFT 6 | |
| 148 #endif // MELODY_E1 | |
| 149 | |
| 150 #if (VOICE_MEMO) || (SPEECH_RECO) | |
| 151 //---------------------------------------- | |
| 152 // Voice memo constant. | |
| 153 //---------------------------------------- | |
| 154 | |
| 155 // Communication DSP<->MCU via the a_du_x buffer: | |
| 156 | |
| 157 // Mask for the bit to indicate: | |
| 158 // in VM play: if the DSP requests a new block | |
| 159 // in VM record: if the DSP has a new block | |
| 160 #define B_BLOCK_READY (TRUE_L<<10) | |
| 161 | |
| 162 // Mask for the bit of the a_du_x buffer to indicate if the block is the speech or noise | |
| 163 #define B_VM_SPEECH (TRUE_L<<15) | |
| 164 | |
| 165 // Size of the a_du_x buffer when the sample is a noise: | |
| 166 #define SC_VM_NOISE_SAMPLE 1 | |
| 167 | |
| 168 // Size of the a_du_x buffer when the sample is a speech: | |
| 169 #define SC_VM_SPEECH_SAMPLE 20 | |
| 170 #endif // VOICE_MEMO || SPEECH_RECO | |
| 171 | |
| 172 #if (L1_VOICE_MEMO_AMR) | |
| 173 //---------------------------------------- | |
| 174 // Voice memo amr constant. | |
| 175 //---------------------------------------- | |
| 176 | |
| 177 #define SC_VM_AMR_HEADER_SIZE 1 | |
| 178 | |
| 179 // Communication DSP<->MCU via the a_du_x buffer: | |
| 180 #define SC_RX_TX_TYPE_MASK (7<<3) | |
| 181 | |
| 182 // Communication DSP<->MCU via d_amms_ul_voc and b_amms_channel_type | |
| 183 #define SC_CHAN_TYPE_MASK 7 | |
| 184 | |
| 185 // RX_TYPE or TX_TYPE (See 06.93) | |
| 186 #define SC_VM_AMR_RXTX_SPEECH_GOOD (0<<3) | |
| 187 #define SC_VM_AMR_RXTX_SPEECH_DEGRADED (1<<3) | |
| 188 #define SC_VM_AMR_RXTX_ONSET (2<<3) | |
| 189 #define SC_VM_AMR_RXTX_SPEECH_BAD (3<<3) | |
| 190 #define SC_VM_AMR_RXTX_SID_FIRST (4<<3) | |
| 191 #define SC_VM_AMR_RXTX_SID_UPDATE (5<<3) | |
| 192 #define SC_VM_AMR_RXTX_SID_BAD (6<<3) | |
| 193 #define SC_VM_AMR_RXTX_NO_DATA (7<<3) | |
| 194 | |
| 195 // sample type for ONSET insertion in NO_SPEECH to SPEECH transition | |
| 196 #define SC_VM_AMR_SPEECH 0 | |
| 197 #define SC_VM_AMR_NOISE 1 | |
| 198 #define SC_VM_AMR_NO_DATA 2 | |
| 199 #define SC_VM_AMR_ONSET 3 | |
| 200 | |
| 201 // Speech channel type | |
| 202 #define SC_VM_AMR_SPEECH_475 0 | |
| 203 #define SC_VM_AMR_SPEECH_515 1 | |
| 204 #define SC_VM_AMR_SPEECH_59 2 | |
| 205 #define SC_VM_AMR_SPEECH_67 3 | |
| 206 #define SC_VM_AMR_SPEECH_74 4 | |
| 207 #define SC_VM_AMR_SPEECH_795 5 | |
| 208 #define SC_VM_AMR_SPEECH_102 6 | |
| 209 #define SC_VM_AMR_SPEECH_122 7 | |
| 210 | |
| 211 // Size of data bits in the a_du_x buffer when the sample is SPEECH | |
| 212 // a_du_x buffer contains header + 2 non-used words after header + data_bits => recorded size is DATA_SIZE + 1 | |
| 213 #define SC_VM_AMR_SPEECH_475_DATA_SIZE 12 | |
| 214 #define SC_VM_AMR_SPEECH_515_DATA_SIZE 13 | |
| 215 #define SC_VM_AMR_SPEECH_59_DATA_SIZE 15 | |
| 216 #define SC_VM_AMR_SPEECH_67_DATA_SIZE 17 | |
| 217 #define SC_VM_AMR_SPEECH_74_DATA_SIZE 19 | |
| 218 #define SC_VM_AMR_SPEECH_795_DATA_SIZE 20 | |
| 219 #define SC_VM_AMR_SPEECH_102_DATA_SIZE 26 | |
| 220 #define SC_VM_AMR_SPEECH_122_DATA_SIZE 31 | |
| 221 | |
| 222 // Size of the a_du_x buffer when the sample is SID_FIRST: | |
| 223 #define SC_VM_AMR_SID_FIRST_DATA_SIZE 5 | |
| 224 | |
| 225 // Size of the a_du_x buffer when the sample is SID_UPDATE: | |
| 226 #define SC_VM_AMR_SID_UPDATE_DATA_SIZE 5 | |
| 227 | |
| 228 // Size of the a_du_x buffer when the sample is SID_BAD: | |
| 229 #define SC_VM_AMR_SID_BAD_DATA_SIZE 5 | |
| 230 | |
| 231 // Size of the a_du_x buffer when the sample is NO_DATA: | |
| 232 #define SC_VM_AMR_NO_DATA_DATA_SIZE 0 | |
| 233 | |
| 234 // Size of the a_du_x buffer when the sample is ONSET: | |
| 235 #define SC_VM_AMR_ONSET_DATA_SIZE 0 | |
| 236 | |
| 237 #endif // L1_VOICE_MEMO_AMR | |
| 238 | |
| 239 #if (SPEECH_RECO) | |
| 240 //---------------------------------------- | |
| 241 // Speech recognition constant. | |
| 242 //---------------------------------------- | |
| 243 | |
| 244 // d_sr_status bit field | |
| 245 #define B_BAD_ACQUISITION (TRUE_L << 8) | |
| 246 #define B_GOOD_ACQUISITION (TRUE_L << 9) | |
| 247 #define B_BAD_UPDATE (TRUE_L << 10) | |
| 248 #define B_GOOD_UPDATE (TRUE_L << 11) | |
| 249 | |
| 250 // d_sr_status VAD indication | |
| 251 #define SC_SR_WORD_MASK 0x00FF | |
| 252 #define SC_SR_WORD_SEARCHING 0 | |
| 253 #define SC_SR_WORD_BEGINNING 1 | |
| 254 #define SC_SR_WORD_ON_GOING 2 | |
| 255 #define SC_SR_WORD_ENDING 3 | |
| 256 #define SC_SR_WORD_DONE 4 | |
| 257 | |
| 258 #endif // SPEECH_RECO | |
| 259 | |
| 260 #if (AEC) | |
| 261 #define B_AEC_ACK (TRUE_L << 0) // Bit set by the MCU to indicate a new AEC settings and | |
| 262 // clear by the DSP to confirm the new settings. | |
| 263 | |
| 264 #define B_AEC_EN (TRUE_L << 1) // enables AEC module | |
| 265 #define B_SPENH_EN (TRUE_L << 2) // enables SPENH module | |
| 266 | |
| 267 | |
| 268 #if (L1_NEW_AEC) | |
| 269 #define B_AEC_VISIBILITY (TRUE_L << 9) // Bit set by the MCU to have internal output values of AEC copied in API | |
| 270 #define SC_AEC_VISIBILITY_SHIFT (9) | |
| 271 #endif | |
| 272 | |
| 273 #endif | |
| 274 | |
| 275 | |
| 276 #if (W_A_DSP_SR_BGD) | |
| 277 #define C_BGD_RECOGN 5 // TEMPORARY: DSP Background recognition task code (also used for bitmaps). | |
| 278 #define C_BGD_ALIGN 6 // TEMPORARY: DSP Background alignement | |
| 279 // bits in d_gsm_bgd_mgt - background task management | |
| 280 #define B_DSPBGD_RECO 1 // start of reco in dsp background | |
| 281 #define B_DSPBGD_UPD 2 // start of alignement update in dsp background | |
| 282 #endif | |
| 283 #if (AUDIO_MODE) | |
| 284 #define B_GSM_ONLY ((TRUE_L << 13) | (TRUE_L << 11)) // GSM normal mode | |
| 285 #define B_BT_CORDLESS (TRUE_L << 12) // Bluetooth cordless mode | |
| 286 #define B_BT_HEADSET (TRUE_L << 14) // Bluetooth headset mode | |
| 287 #endif | |
| 288 | |
| 289 #define SC_AUDIO_MCU_API_BEGIN_ADDRESS (0xFFD00000) // Start address of the API memory in MCU side | |
| 290 #define SC_AUDIO_DSP_API_BEGIN_ADDRESS (0x0800) // Start address o fthe API memory in DSP side | |
| 291 | |
| 292 #if (MELODY_E2) | |
| 293 // Number of oscillator available in the melody E2 | |
| 294 #define SC_MELODY_E2_NUMBER_OF_OSCILLATOR (16) | |
| 295 | |
| 296 // Code of extension for data=time | |
| 297 #define SC_TIME_CODE_OF_EXTENSION (1) | |
| 298 | |
| 299 // Position of the GlobalTimeFactor parameter | |
| 300 #define SC_MELODY_E2_GLOBALTIMEFACTOR_MASK (0xFF) | |
| 301 #define SC_MELODY_E2_GLOBALTIMEFACTOR_SHIFT (0) | |
| 302 | |
| 303 // Position of the Number of instrument parameter | |
| 304 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_MASK (0xFF) | |
| 305 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_SHIFT (0) | |
| 306 | |
| 307 // Position of the extension flag | |
| 308 #define SC_MELODY_E2_EXTENSION_FLAG_MASK (0x80) | |
| 309 #define SC_MELODY_E2_EXTENSION_FLAG_SHIFT (7) | |
| 310 | |
| 311 // Position of the code of extension | |
| 312 #define SC_MELODY_E2_CODE_OF_EXTENSION_MASK (0x70) | |
| 313 #define SC_MELODY_E2_CODE_OF_EXTENSION_SHIFT (4) | |
| 314 | |
| 315 // Position of data time | |
| 316 #define SC_MELODY_E2_DATA_TIME_MSB_MASK (0x07) | |
| 317 #define SC_MELODY_E2_DATA_TIME_MSB_SHIFT (0) | |
| 318 | |
| 319 // Position of data time | |
| 320 #define SC_MELODY_E2_DATA_TIME_LSB_MASK (0xFF00) | |
| 321 #define SC_MELODY_E2_DATA_TIME_LSB_SHIFT (8) | |
| 322 | |
| 323 // Position of the Delta Time | |
| 324 #define SC_MELODY_E2_DELTA_TIME_MASK (0x7F) | |
| 325 #define SC_MELODY_E2_DELTA_TIME_SHIFT (0) | |
| 326 | |
| 327 // Mask of the semaphore | |
| 328 #define SC_MELODY_E2_SEMAPHORE_MASK (0x0001) | |
| 329 | |
| 330 // Maximum size of the header of the melody E2 | |
| 331 #define SC_MELODY_E2_MAXIMUM_HEADER_SIZE (3 + SC_AUDIO_MELODY_E2_MAX_NUMBER_OF_INSTRUMENT) | |
| 332 | |
| 333 // Maximum number of extension | |
| 334 #define SC_MELODY_E2_MAXIMUM_NUMBER_OF_EXTENSION (2) | |
| 335 #endif // MELODY_E2 | |
| 336 | |
| 337 // Selection of the melody format | |
| 338 #define NO_MELODY_SELECTED (0) | |
| 339 #define MELODY_E0_SELECTED (1) | |
| 340 #define MELODY_E1_SELECTED (2) | |
| 341 #define MELODY_E2_SELECTED (3) | |
| 342 | |
| 343 #endif // AUDIO_TASK | |
| 344 | |
| 345 #if (DSP == 17) || (DSP == 32) | |
| 346 #define B_FIR_START (TRUE_L << 0) // Bit set by the MCU to start the FIR task for the DSP code 32 and 17. | |
| 347 #endif | |
| 348 | |
| 349 #define B_FIR_LOOP (TRUE_L << 1) // Bit set by the MCU to close the loop between the audio UL and DL path. | |
| 350 // This features is used to find the FIR coefficient. |
