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comparison src/cs/layer1/cfile/l1_init.c @ 0:4e78acac3d88

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src/{condat,cs,gpf,nucleus}: import from Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 16 Oct 2020 06:23:26 +0000
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children 0ed36de51973
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-1:000000000000 0:4e78acac3d88
1 /************ Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_INIT.C
4 *
5 * Filename l1_init.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_INIT_C
11
12 #include "l1_confg.h"
13
14 #define W_A_DSP_PR20037 1 /* FreeCalypso */
15
16 #if (CODE_VERSION == SIMULATION)
17 #include <string.h>
18 #include "l1_types.h"
19 #include "sys_types.h"
20 #include "l1_const.h"
21 #include "l1_time.h"
22 #include "l1_signa.h"
23
24 #if TESTMODE
25 #include "l1tm_defty.h"
26 #endif
27 #if (AUDIO_TASK == 1)
28 #include "l1audio_const.h"
29 #include "l1audio_cust.h"
30 #include "l1audio_defty.h"
31 #endif
32 #if (L1_GTT == 1)
33 #include "l1gtt_const.h"
34 #include "l1gtt_defty.h"
35 #endif
36
37 #if (L1_MP3 == 1)
38 #include "l1mp3_defty.h"
39 #endif
40
41 #if (L1_MIDI == 1)
42 #include "l1midi_defty.h"
43 #endif
44 //ADDED FOR AAC
45 #if (L1_AAC == 1)
46 #include "l1aac_defty.h"
47 #endif
48 #if (L1_DYN_DSP_DWNLD == 1)
49 #include "l1_dyn_dwl_proto.h"
50 #endif
51
52 #include "l1_defty.h"
53 #include "cust_os.h"
54 #include "l1_msgty.h"
55 #include "l1_varex.h"
56 #include "l1_proto.h"
57 #include "l1_mftab.h"
58 #include "l1_tabs.h"
59 #include "l1_ver.h"
60 #include "ulpd.h"
61
62 #include "l1_proto.h"
63
64 #if L1_GPRS
65 #include "l1p_cons.h"
66 #include "l1p_msgt.h"
67 #include "l1p_deft.h"
68 #include "l1p_vare.h"
69 #include "l1p_tabs.h"
70 #include "l1p_macr.h"
71 #include "l1p_ver.h"
72 #endif
73
74 #if TESTMODE
75 #include "l1tm_ver.h"
76 #endif
77
78 #include <stdio.h>
79 #include "sim_cfg.h"
80 #include "sim_cons.h"
81 #include "sim_def.h"
82 #include "sim_var.h"
83
84 #else // NO SIMULATION
85
86 #include <string.h>
87 #include "tm_defs.h"
88 #include "l1_types.h"
89 #include "sys_types.h"
90 #include "leadapi.h"
91 #include "l1_const.h"
92 #include "l1_macro.h"
93 #include "l1_time.h"
94 #include "l1_signa.h"
95 #if (AUDIO_TASK == 1)
96 #include "l1audio_const.h"
97 #include "l1audio_cust.h"
98 #include "l1audio_defty.h"
99 #endif
100
101
102 #include "spi_drv.h"
103 #include "abb.h"
104 #if (ANLG_FAM != 11)
105 #include "abb_core_inth.h"
106 #endif
107
108 #if TESTMODE
109 #include "l1tm_defty.h"
110 #endif
111
112 #if (L1_GTT == 1)
113 #include "l1gtt_const.h"
114 #include "l1gtt_defty.h"
115 #endif
116
117 #if (L1_MP3 == 1)
118 #include "l1mp3_defty.h"
119 #endif
120
121 #if (L1_MIDI == 1)
122 #include "l1midi_defty.h"
123 #endif
124 //ADDED FOR AAC
125 #if (L1_AAC == 1)
126 #include "l1aac_defty.h"
127 #endif
128 #if (L1_DYN_DSP_DWNLD == 1)
129 #include "l1_dyn_dwl_proto.h"
130 #endif
131
132 #include "l1_defty.h"
133 #include "cust_os.h"
134 #include "l1_msgty.h"
135 #include "l1_varex.h"
136 #include "l1_proto.h"
137 #include "l1_mftab.h"
138 #include "l1_tabs.h"
139 #include "l1_ver.h"
140 #include "tpudrv.h"
141
142 #if (CHIPSET == 12) || (CHIPSET == 15)
143 #include "sys_inth.h"
144 #else
145 #include "mem.h"
146 #include "inth.h"
147 #include "dma.h"
148 #include "iq.h"
149 #endif
150
151 #include "clkm.h"
152 #include "rhea_arm.h"
153 #include "ulpd.h"
154
155 #include "l1_proto.h"
156
157 #if L1_GPRS
158 #include "l1p_cons.h"
159 #include "l1p_msgt.h"
160 #include "l1p_deft.h"
161 #include "l1p_vare.h"
162 #include "l1p_tabs.h"
163 #include "l1p_macr.h"
164 #include "l1p_ver.h"
165 #endif
166
167 #if TESTMODE
168 #include "l1tm_ver.h"
169 #endif
170
171 #endif // NOT SIMULATION
172
173
174
175 #if (RF_FAM == 61)
176 #if (DRP_FW_EXT==0)
177 #include "drp_drive.h"
178 #include "drp_api.h"
179 #include "l1_rf61.h"
180 #include "apc.h"
181 #else
182 #include "l1_rf61.h"
183 #include "l1_drp_inc.h"
184 #endif
185 #endif
186
187
188 #if (RF_FAM == 60)
189 #include "drp_drive.h"
190 #include "drp_api.h"
191 #include "l1_rf60.h"
192 #endif
193
194 #if (TRACE_TYPE == 1)||(TRACE_TYPE == 4)
195 #include "l1_trace.h"
196 #endif
197
198 #include <string.h>
199 #include <stdio.h>
200
201 #if (ANLG_FAM == 11)
202 #include "bspTwl3029_I2c.h"
203 #include "bspTwl3029_Aud_Map.h"
204 #include "bspTwl3029_Madc.h"
205 #endif
206
207 #if (RF_FAM == 61)
208 //OMAPS148175
209 #include "l1_drp_if.h"
210 #include "drp_main.h"
211 #endif
212
213 #if (ANLG_FAM == 11)
214 #if (L1_MADC_ON == 1)
215 extern BspTwl3029_MadcResults l1_madc_results;
216 extern void l1a_madc_callback(void);
217 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
218 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC
219 #endif
220 #endif
221
222 #if (AUDIO_DEBUG == 1)
223 extern UWORD8 audio_reg_read_status;
224 #endif
225
226 #endif
227
228 #if (AUDIO_TASK == 1)
229 /**************************************/
230 /* External audio prototypes */
231 /**************************************/
232 extern void l1audio_initialize_var (void);
233 #endif
234
235 extern void l1audio_dsp_init (void);
236 extern void initialize_wait_loop(void);
237
238 #if (L1_GPRS)
239 // external functions from GPRS implementation
240 void initialize_l1pvar(void);
241 void l1pa_reset_cr_freq_list(void);
242 #endif // L1_GPRS
243 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38)|| (DSP == 39))&& (CODE_VERSION != SIMULATION))
244 extern void l1_api_dump(void);
245 #endif
246
247 #if (TRACE_TYPE==3)
248 void reset_stats();
249 #endif // TRACE_TYPE
250
251 #if (L1_GTT == 1)
252 extern void l1gtt_initialize_var(void);
253 #endif
254
255 #if (L1_MP3 == 1)
256 extern void l1mp3_initialize_var(void);
257 #endif
258
259 #if (L1_MIDI == 1)
260 extern void l1midi_initialize_var(void);
261 #endif
262 //ADDED FOR AAC
263 #if (L1_AAC == 1)
264 extern void l1aac_initialize_var(void);
265 #endif
266
267 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
268 extern void L1_trace_string(char *s);
269 #endif
270
271 #if (RF_FAM == 60 || RF_FAM == 61)
272 extern const UWORD8 drp_ref_sw[] ;
273 extern T_DRP_REGS_STR *drp_regs;
274 extern T_DRP_SRM_API* drp_srm_api;
275
276 extern T_DRP_SW_DATA drp_sw_data_calib;
277 extern T_DRP_SW_DATA drp_sw_data_init;
278
279 #endif
280
281 /*-------------------------------------------------------*/
282 /* l1_dsp_init() */
283 /*-------------------------------------------------------*/
284 /* Parameters : */
285 /* Return : */
286 /* Functionality : */
287 /*-------------------------------------------------------*/
288 void l1_dsp_init(void)
289 {
290 //int i;-OMAPS90550- new
291 #if (CODE_VERSION == SIMULATION)
292 // L1S <-> DSP communication...
293 //====================================================
294 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb);
295 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[0]);
296 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[0]);
297 l1s_dsp_com.dsp_param_ptr = &(buf.param);
298 l1s_dsp_com.dsp_w_page = 0;
299 l1s_dsp_com.dsp_r_page = 0;
300 l1s_dsp_com.dsp_r_page_used = 0;
301
302 #if (L1_GPRS)
303 l1ps_dsp_com.pdsp_ndb_ptr = &(buf.ndb_gprs);
304 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[0]);
305 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[0]);
306 l1ps_dsp_com.pdsp_param_ptr = &(buf.param_gprs);
307 #endif
308
309 // Reset DSP page bit and DSP enable bit...
310 //====================================================
311 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF;
312 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0;
313
314 // Set EOTD bit if required
315 //====================================================
316 #if (L1_EOTD ==1)
317 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
318 #endif
319
320
321 #else // NO SIMULATION
322
323 // L1S <-> DSP communication...
324 //====================================================
325 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
326 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0;
327 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0;
328 l1s_dsp_com.dsp_param_ptr = (T_PARAM_MCU_DSP *) PARAM_ADR;
329 l1s_dsp_com.dsp_w_page = 0;
330 l1s_dsp_com.dsp_r_page = 0;
331 l1s_dsp_com.dsp_r_page_used = 0;
332
333 #if (DSP == 38) || (DSP == 39)
334 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *)DB_COMMON_W_PAGE_0;
335 #endif
336
337 /* DSP CPU load measurement */
338 #if (DSP == 38) || (DSP == 39)
339 l1s_dsp_com.dsp_cpu_load_db_w_ptr = (T_DB_MCU_TO_DSP_CPU_LOAD *)DSP_CPU_LOAD_DB_W_PAGE_0;
340 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_CTRL))) = (API)0x0001; // enable DSP CPU load measurement
341 #endif
342
343 #if (L1_GPRS)
344 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
345 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS;
346 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS;
347 l1ps_dsp_com.pdsp_param_ptr = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
348 #endif
349
350 #if (DSP_DEBUG_TRACE_ENABLE == 1)
351 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0;
352 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1;
353 #endif
354
355 // Reset DSP page bit and DSP enable bit...
356 //====================================================
357
358 (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL;
359
360 #if (DSP >= 33)
361 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
362 #else
363 l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
364 #endif
365
366 // NDB init : Reset buffers and set flags...
367 //====================================================
368 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = FB_MODE_1;
369 l1s_dsp_com.dsp_ndb_ptr->d_fb_det = FALSE; // D_FB_DET =0
370 l1s_dsp_com.dsp_ndb_ptr->a_cd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
371 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[0] = 0; // BLUD = 0
372 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[2] = 0xffff; // NERR = 0xffff
373 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[0] = 0; // BLUD = 0
374 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[2] = 0xffff; // NERR = 0xffff
375 l1s_dsp_com.dsp_ndb_ptr->a_du_0[0] = 0; // BLUD = 0
376 l1s_dsp_com.dsp_ndb_ptr->a_du_0[2] = 0xffff; // NERR = 0xffff
377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[0] = 0; // BLUD = 0
378 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff
379 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
380 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff
381 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0;
382
383 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
384 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11)
385 #endif
386
387 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
388 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits
389 #endif
390 #if (ANLG_FAM == 11)
391 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits
392 #endif
393
394 #if (DSP == 32)
395 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2;
396 #endif // OP_WCP
397
398 l1s_dsp_com.dsp_ndb_ptr->a_sch26[0] = (1<<B_SCH_CRC);// B_SCH_CRC =1, BLUD =0
399 l1audio_dsp_init();
400
401 #if IDS
402 l1s_dsp_com.dsp_ndb_ptr->d_ra_conf = 0; // IDS
403 l1s_dsp_com.dsp_ndb_ptr->d_ra_act = 0; // IDS
404 l1s_dsp_com.dsp_ndb_ptr->d_ra_test = 0; // IDS
405 l1s_dsp_com.dsp_ndb_ptr->d_ra_statu = 0; // IDS
406 l1s_dsp_com.dsp_ndb_ptr->d_ra_statd = 0; // IDS
407 l1s_dsp_com.dsp_ndb_ptr->d_fax = 0; // IDS
408 #endif
409
410 #if(RF_FAM != 61)
411 // interrupt rif TX on FIFO <= threshold with threshold = 0
412 l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179;
413 #else
414 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny
415
416 #endif
417
418 #if (DSP >= 33)
419 // Initialize V42b variables
420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0;
421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0;
422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0;
423 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0;
424 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control = 0;
425 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control_sema = 0;
426
427 #if !(W_A_DSP_SR_BGD)
428 // Initialize background control variable to No background. Background tasks can be launch in GPRS
429 // as in GSM.
430 l1s_dsp_com.dsp_ndb_ptr->d_max_background = 0;
431 #endif
432
433 #if (L1_GPRS)
434 #if (DSP == 36) || (DSP == 37)
435 // Initialize GEA module
436 l1ps_dsp_com.pdsp_ndb_ptr->d_gea_mode = 0;
437 #endif
438 #endif
439
440 #else
441 #if (L1_GPRS)
442 // Initialize background control variable to No background
443 l1ps_dsp_com.pdsp_ndb_ptr->d_max_background = 0;
444 #endif
445 #endif
446
447 #if (L1_GPRS)
448 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER;
449
450 // Initialize the poll response buffer to "no poll request"
451 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE;
452 #else // L1_GPRS
453 #if (DSP >= 31)
454 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER;
455 #endif
456 #endif // L1_GPRS
457
458 // Set EOTD bit if required
459 //=============================================
460 #if (L1_EOTD ==1)
461 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
462 #endif // L1_EOTD
463
464 #if (DSP == 33)
465 #if DCO_ALGO
466 // Set DCO bit
467 if (l1_config.params.dco_enabled == TRUE)
468 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
469 #endif
470 #endif
471
472 // DCO algo in case of DSP 17/32
473 #if (DCO_ALGO == 1)
474 #if ((DSP == 17)||(DSP == 32))
475 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
476 #endif // DSP
477 #endif // DCO_ALGO
478
479 #if (DSP >= 34)
480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0;
481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0;
482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0;
483 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0;
484 #endif
485
486 #if (DSP >= 35)
487 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS
488 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS
489 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS
490 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS
491 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS
492 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_ahs = 150; // thresh detection SID frames AHS
493 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_marker = 500; // thresh detection RATSCCH MARKER
494 l1s_dsp_com.dsp_ndb_ptr->d_thr_sp_dgr = 3; // thresh detection SPEECH DEGRADED/NO_DATA
495 l1s_dsp_com.dsp_ndb_ptr->d_thr_soft_bits = 0; // thresh detection SPEECH DEGRADED/NO_DATA
496 #endif
497
498 #if ((DSP >= 36) && (AMR_THRESHOLDS_WORKAROUND == 1))
499 // init of the afs thresholds parameters
500 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[0]=0;
501 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[1]=0;
502 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[2]=0;
503 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[3]=0;
504 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[4]=0;
505 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[5]=0;
506 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[6]=0;
507 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[7]=1500;
508
509 // init of the ahs thresholds parameters
510 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[0]=1500;
511 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[1]=1500;
512 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[2]=1500;
513 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[3]=1500;
514 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[4]=1500;
515 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[5]=1500;
516 #endif
517
518 #if (DSP >= 34)
519 // init of of the threshold for USF detection
520 #if 1 /* match TCS211 object */
521 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2140;
522 #elif (L1_FALSE_USF_DETECTION == 1)
523 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2300;
524 #else
525 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0;
526 #endif
527 #endif
528
529 #if (CHIPSET == 12) || (CHIPSET == 15)
530 #if (DSP >= 35)
531 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0;
532 #endif
533 #endif
534
535 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto
536 #if (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
537 // Note: for locosto there is only one MCSI port
538 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = MCSI_PORT1;
539 #endif
540
541 #if(DSP == 36) || (DSP == 37)
542 l1s_dsp_com.dsp_ndb_ptr->d_vol_ul_level = 0x1000;
543 l1s_dsp_com.dsp_ndb_ptr->d_vol_dl_level = 0x1000;
544 l1s_dsp_com.dsp_ndb_ptr->d_vol_speed = 0x68;
545 l1s_dsp_com.dsp_ndb_ptr->d_sidetone_level = 0;
546 #endif
547 #endif // ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)))
548
549 // DB Init DB : Reset all pages, set TX power and reset SCH buffer...
550 //====================================================
551 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_0);
552 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_1);
553 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_0);
554 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_1);
555 #if (DSP == 38) || (DSP == 39)
556 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0);
557 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_1);
558 #endif
559
560 #endif // NO_SIMULATION
561
562 #if ((DSP==17)||(DSP == 32))
563 // init the DC offset values
564 l1s_dsp_com.dsp_ndb_ptr->d_dco_type = 0x0000; // Tide off
565 l1s_dsp_com.dsp_ndb_ptr->p_start_IQ = 0x0000;
566 l1s_dsp_com.dsp_ndb_ptr->d_level_off = 0x0000;
567 l1s_dsp_com.dsp_ndb_ptr->d_dco_dbg = 0x0000;
568 l1s_dsp_com.dsp_ndb_ptr->d_tide_resa = 0x0000;
569 #endif
570
571 //Initialize DSP DCO
572 #if (((DSP == 38) || (DSP == 39)) && (RF_FAM == 61))
573 l1s_dsp_com.dsp_ndb_ptr->d_dco_samples_per_symbol = C_DCO_SAMPLES_PER_SYMBOL;
574 l1s_dsp_com.dsp_ndb_ptr->d_dco_fcw = C_DCO_FCW;
575
576 // APCDEL1 will be initialized on rach only ....
577 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
578 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
579 // APCCTRL2 alone initialize on the next TDMA frame possible
580 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
581
582 l1dapc_init_ramp_tables();
583
584 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 ))
585
586 /* Chase combining feature flag Initialise */
587 l1s_dsp_com.dsp_ndb_ptr->d_chase_comb_ctrl |= 0x0001;
588 #endif /* FF_REPEATED_SACCH or FF_REPEATED_DL_FACCH */
589
590 #endif // DSP == 38
591
592 // Intialize the AFC
593 #if (DSP == 38) || (DSP == 39)
594 #if (CODE_VERSION != SIMULATION)
595 l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS;
596 #endif
597
598 #if (L1_DRP_IQ_SCALING == 1)
599 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1;
600 #else
601 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0;
602 #endif
603 #endif
604
605 }
606
607 /*-------------------------------------------------------*/
608 /* l1_tpu_init() */
609 /*-------------------------------------------------------*/
610 /* Parameters : */
611 /* Return : */
612 /* Functionality : */
613 /*-------------------------------------------------------*/
614 void l1_tpu_init(void)
615 {
616 #if (CODE_VERSION == SIMULATION)
617 // L1S -> TPU communication...
618 //=============================
619 l1s_tpu_com.tpu_w_page = 0;
620 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
621 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
622 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
623 l1s_tpu_com.offset = &(hw.offset);
624
625 // Reset TPU.
626 //=============================
627 *(l1s_tpu_com.offset) = 0;
628 *(l1s_tpu_com.reg_com_int) = 0;
629 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
630 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
631 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
632 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
633 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
634
635 // Init. OFFSET and SYNC registers
636 //================================
637 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
638 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
639 l1dtpu_end_scenario(); // Close TPU scenario
640
641 #else
642 // bit TPU_RESET set
643 // OFFSET and SYNCHRO initialized at 0
644 // TSP_ACT bits reset
645 // Sleep added and TPU_ENABLE set...
646 l1dmacro_init_hw();
647
648 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
649 #endif
650 }
651
652 void l1_tpu_init_light(void)
653 {
654 #if (CODE_VERSION == SIMULATION)
655 // L1S -> TPU communication...
656 //=============================
657 l1s_tpu_com.tpu_w_page = 0;
658 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
659 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
660 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
661 l1s_tpu_com.offset = &(hw.offset);
662
663 // Reset TPU.
664 //=============================
665 *(l1s_tpu_com.offset) = 0;
666 *(l1s_tpu_com.reg_com_int) = 0;
667 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
668 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
669 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
670 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
671 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
672
673 // Init. OFFSET and SYNC registers
674 //================================
675 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
676 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
677 l1dtpu_end_scenario(); // Close TPU scenario
678
679 #else
680 // bit TPU_RESET set
681 // OFFSET and SYNCHRO initialized at 0
682 // TSP_ACT bits reset
683 // Sleep added and TPU_ENABLE set...
684 l1dmacro_init_hw_light();
685
686 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
687 #endif
688 }
689
690 /*-------------------------------------------------------*/
691 /* l1_abb_power_on() */
692 /*-------------------------------------------------------*/
693 /* Parameters : */
694 /* Return : */
695 /* Functionality : */
696 /* Initialize the global structure for spi communication */
697 /* with ABB. */
698 /* Set up ABB connection (CLK 13M free) */
699 /* Aknowledge the ABB status register */
700 /* Configure ABB modules */
701 /* Program the ramp parameters into the NDB */
702 /* Load in the NDB registers' value to be programmed in */
703 /* ABB at first communication it */
704 /*-------------------------------------------------------*/
705
706 //Locosto This funciton would change drastically due to Triton introduction and instead of SPI we have i2c
707 void l1_abb_power_on(void)
708 {
709 #if (CODE_VERSION != SIMULATION)
710 #if (CHIPSET != 15)
711 T_SPI_DEV *Abb;
712 T_SPI_DEV init_spi_device;
713 UWORD16 Abb_Status;
714 T_NDB_MCU_DSP * dsp_ndb_ptr;
715
716 Abb = &init_spi_device; /* Pointer initialization to device communication structure */
717 Abb->PrescVal = SPI_CLOCK_DIV_1; /* ABB transmission parameters initialization */
718 Abb->DataTrLength = SPI_WNB_15;
719 Abb->DevAddLength = 5;
720 Abb->DevId = ABB;
721 Abb->ClkEdge = SPI_CLK_EDG_RISE;
722 Abb->TspEnLevel = SPI_NTSPEN_NEG_LEV;
723 Abb->TspEnForm = SPI_NTSPEN_LEV_TRIG;
724
725 SPI_InitDev(Abb); /* Initialize the spi to work with ABB */
726
727 ABB_free_13M(); /* Set up Abb connection (CLK 13M free).*/
728 Abb_Status = ABB_Read_Status(); /* Aknowledge the Abb status register. */
729
730 /*------------------------------------------------------------------*/
731 /* Add here SW to manage Abb VRPCSTS status register informations */
732 /*------------------------------------------------------------------*/
733
734 ABB_Read_Register_on_page(PAGE0,ITSTATREG); /* Aknowledge the interrupt status register */
735 /* to clear any pending interrupt */
736
737 ABB_on(AFC | MADC, l1a_l1s_com.recovery_flag);
738
739 // ADC init: Configuration of the channels to be converted and enable the ADC Interrupt
740 ABB_Conf_ADC(ALL,EOC_INTENA);
741
742 //in case of reset due to a recovery process do not create the HISR
743 if (l1a_l1s_com.recovery_flag == FALSE)
744 {
745 Create_ABB_HISR();
746 }
747
748 // Load RAMP up/down in NDB memory...
749 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
750
751 if (l1_config.tx_pwr_code == 0)
752 {
753 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
754 0 /* not used */,
755 0 /* not used */,
756 1 /* arbitrary value for arfcn*/);
757 }
758 else
759 {
760 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
761 5 /* arbitrary value working in any case */,
762 5 /* arbitrary value working in any case */,
763 1 /* arbitrary value for arfcn*/);
764 }
765 #endif
766
767
768 #if (ANLG_FAM == 1)
769 // Omega registers values will be programmed at 1st DSP communication interrupt
770
771 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
772 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
773 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
774 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
775 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
776 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
777 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
778 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
779 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
780 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
781 dsp_ndb_ptr->d_vbctrl = l1_config.params.vbctrl; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
782
783 // APCDEL1 will be initialized on rach only ....
784 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
785
786 #if (DSP >= 33)
787 // To increase the robustness the IOTA register are reseted to 0
788 // if OMEGA, NAUSICA is used
789 dsp_ndb_ptr->d_bulgcal = 0x0000;
790 dsp_ndb_ptr->d_vbctrl2 = 0x0000;
791 dsp_ndb_ptr->d_apcdel2 = 0x0000;
792 #endif
793 #endif
794 #if (ANLG_FAM == 2)
795 // Iota registers values will be programmed at 1st DSP communication interrupt
796
797 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
798 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
799 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
800 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
801 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
802 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
803 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
804 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
805 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
806 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
807 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
808 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
809 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
810
811 // APCDEL1 will be initialized on rach only ....
812 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
813 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
814 #endif
815 #if (ANLG_FAM == 3)
816 // Syren registers values will be programmed at 1st DSP communication interrupt
817
818 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
819 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
820 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
821 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
822 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
823 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
824 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
825 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
826 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
827 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
828 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
829 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0
830 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
831
832 // APCDEL1 will be initialized on rach only ....
833 dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
834 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
835
836 // Additional registers management brought by SYREN
837 dsp_ndb_ptr->d_vbpop = l1_config.params.vbpop; // HSOAUTO enabled only
838 dsp_ndb_ptr->d_vau_delay_init = l1_config.params.vau_delay_init; // vaud_init_delay init 2 frames
839 dsp_ndb_ptr->d_vaud_cfg = l1_config.params.vaud_cfg; // Init to zero
840 dsp_ndb_ptr->d_vauo_onoff = l1_config.params.vauo_onoff; // Init to zero
841 #if ((L1_AUDIO_MCU_ONOFF == 1)&&(OP_L1_STANDALONE == 1)&&(CHIPSET == 12))
842 ABB_Write_Register_on_page(PAGE1, VAUOCTRL, 0x0015A);
843 #endif // E Sample testing of audio on off
844 dsp_ndb_ptr->d_vaus_vol = l1_config.params.vaus_vol; // Init to zero
845 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero
846 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense)
847
848 #endif
849
850 #if (ANLG_FAM == 11)
851 // The following settings need to be done only in L1 StandALoen as PSP would
852 // do in the case of full PS Build...
853
854 //Set the CTRL3 register
855 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
856 l1_config.params.ctrl3,NULL);
857
858 #if (OP_L1_STANDALONE == 1)
859 // THESE REGISTERS ARE INITIALIZED IN STANDALONE AND PS BUILDS FOR AUDIO PATH
860
861 // ************ START REG INIT FOR PS build/STANDALONE *************
862 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_TOGB_OFFSET,
863 0x15,NULL);
864 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VULGAIN_OFFSET,
865 l1_config.params.vulgain,NULL);
866 //Set the VDLGAIN register
867 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VDLGAIN_OFFSET,
868 l1_config.params.vdlgain,NULL);
869 //Set the SIDETONE register
870 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_SIDETONE_OFFSET,
871 l1_config.params.sidetone,NULL);
872 //Set the CTRL1 register
873 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL1_OFFSET,
874 l1_config.params.ctrl1,NULL);
875 //Set the CTRL2 register
876 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL2_OFFSET,
877 l1_config.params.ctrl2,NULL);
878
879 //Set the CTRL4 register
880 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL4_OFFSET,
881 l1_config.params.ctrl4,NULL);
882 //Set the CTRL5 register
883 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL5_OFFSET,
884 l1_config.params.ctrl5,NULL);
885 //Set the CTRL6 register
886 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL6_OFFSET,
887 l1_config.params.ctrl6,NULL);
888 //Set the POPAUTO register
889 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_POPAUTO_OFFSET,
890 l1_config.params.popauto,NULL);
891
892 // ************ END REG INIT FOR PS build/STANDALONE ****************
893
894
895
896 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
897 l1_config.params.outen1,NULL);
898 //Set the OUTEN2 register
899 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
900 l1_config.params.outen2,NULL);
901 //Set the OUTEN3 register
902 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
903 l1_config.params.outen3,NULL);
904
905
906
907 //Set the AUDLGAIN register
908 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDLGAIN_OFFSET,
909 l1_config.params.aulga,NULL);
910 //Set the AUDRGAIN register
911 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDRGAIN_OFFSET,
912 l1_config.params.aurga,NULL);
913 #endif
914
915
916 #if (OP_L1_STANDALONE == 1)
917 #if (L1_MADC_ON == 1)
918 //MADC Real time initialization for all the 11 ADCs
919 bspTwl3029_Madc_enableRt( NULL, 0x7ff, l1a_madc_callback, &l1_madc_results);
920 #endif
921 #endif
922
923 #endif
924 #endif //CODE_VERSION != SIMULATION
925 }
926
927 /*-------------------------------------------------------*/
928 /* l1_pwr_mgt_init() */
929 /*-------------------------------------------------------*/
930 /* Parameters : */
931 /* ------------- */
932 /* Return : */
933 /* ------------- */
934 /* Description : */
935 /* ------------- */
936 /* This routine is used to initialize the gauging */
937 /* related variables. */
938 /*-------------------------------------------------------*/
939 void l1_pwr_mgt_init(void)
940 {
941
942 //++++++++++++++++++++++++++++++++++++++++++
943 // Power management variables
944 //++++++++++++++++++++++++++++++++++++++++++
945
946 // flags for wake-up ....
947 l1s.pw_mgr.Os_ticks_required = FALSE;
948 l1s.pw_mgr.frame_adjust = FALSE;
949 #if 0 /* not present in TCS211 */
950 l1s.pw_mgr.wakeup_time = 0;
951 #endif
952
953 // variables for sleep ....
954 l1s.pw_mgr.sleep_duration = 0;
955 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP;
956 l1s.pw_mgr.modules_status = 0; // all clocks ON
957 l1s.pw_mgr.paging_scheduled = FALSE;
958
959 #if 0 /* not present in TCS211 */
960 // variable for afc bypass mode
961 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE;
962 #endif
963
964 // 32 Khz gauging ....
965 l1s.pw_mgr.gaug_count = 0;
966 l1s.pw_mgr.enough_gaug = FALSE;
967 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
968 #if 0 /* not present in TCS211 */
969 l1s.force_gauging_next_paging_due_to_CCHR = 0;
970 #endif
971 l1s.pw_mgr.gauging_task = INACTIVE;
972
973 // GAUGING duration
974 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
975 if (l1_config.dpll <8 )
976 l1s.pw_mgr.gaug_duration = 9; // 9 frames (no more CTRL with DSP)
977 else // with a dpll >= 104Mhz the HF counter is too small: gauging limitation to 6 frames.
978 #if(CHIPSET == 15)
979 // Gauging duration could be reduced to 4 frames (from 5 frames) as fast paging (FF_L1_FAST_DECODING) is available
980 l1s.pw_mgr.gaug_duration = 4; // 4 frames
981 #else
982 l1s.pw_mgr.gaug_duration = 6; // 6 frames
983 #endif
984 #else
985 l1s.pw_mgr.gaug_duration = 11; // 1CTRL + 9 frames +1CTRL
986 #endif
987
988
989 //-------------------------------------------------
990 // INIT state:
991 // 32.768Khz is in the range [-500 ppm,+100 ppm]
992 // due to temperature variation.
993 // LF_100PPM = 32.7712768 Khz
994 // LF_500PPM = 32.751616 Khz
995 //
996 // ACQUIS STATE :
997 // 32.768Khz variations allowed from INIT value
998 // are [-50 ppm,+50ppm]. Same delta on ideal 32khz
999 // during 9 frames (gauging duration) represents 1348*T32.
1000 // LF_50PPM = 32.7696384 Khz
1001 // 1348/32.768 - 1348/32.7696384 = 0.002056632 ms
1002 // At 78 Mhz it means : 0.002056632ms/0.000012820513ms= 160 T
1003 //
1004 // UPDATE state :
1005 // allowed variations are [-6 ppm,+6ppm] jitter
1006 // LF_6PPM = 32.76819661 Khz
1007 // 1348/32.768 - 1348/32.76819661 = 0.00024691 ms
1008 // At 78 Mhz it means : 0.00024691 / 0.000012820513ms= 19 T
1009 //
1010 // 78 Mhz 65 Mhz 84.5 Mhz
1011 // ===========================
1012 // C_CLK_MIN 2380 1983 2578
1013 // C_CLK_INIT_MIN 8721 29113 31293
1014 // C_CLK_MAX 2381 1984 2580
1015 // C_CLK_INIT_MAX 36823 41608 1662
1016 // C_DELTA_HF_ACQUIS 160 130 173
1017 // C_DELTA_HF_UPDATE 19 15 20
1018 //-------------------------------------------------
1019 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
1020 l1s.pw_mgr.c_clk_min = C_CLK_MIN;
1021 l1s.pw_mgr.c_clk_init_min = C_CLK_INIT_MIN;
1022 l1s.pw_mgr.c_clk_max = C_CLK_MAX;
1023 l1s.pw_mgr.c_clk_init_max = C_CLK_INIT_MAX;
1024 l1s.pw_mgr.c_delta_hf_acquis = C_DELTA_HF_ACQUIS;
1025 l1s.pw_mgr.c_delta_hf_update = C_DELTA_HF_UPDATE;
1026 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1027 // 78000/32.7712768 = 2380.13308
1028 l1s.pw_mgr.c_clk_min = (UWORD32)((l1_config.dpll*MCUCLK)/LF_100PPM);
1029 // 0.13308*2^16
1030 #if 0 /* LoCosto version */
1031 l1s.pw_mgr.c_clk_init_min =(UWORD32) ((UWORD32)((UWORD32)(((UWORD32)(l1_config.dpll*MCUCLK))-
1032 (l1s.pw_mgr.c_clk_min*LF_100PPM))*
1033 65536)/LF_100PPM); //omaps00090550
1034 #else /* TSM30 version */
1035 l1s.pw_mgr.c_clk_init_min = (UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1036 (double)(l1s.pw_mgr.c_clk_min*LF_100PPM))*
1037 65536)/LF_100PPM;
1038 #endif
1039 // 78000/32.751616 = 2381.561875
1040 l1s.pw_mgr.c_clk_max = (UWORD32)((l1_config.dpll*MCUCLK)/LF_500PPM); //omaps00090550
1041 // 0.561875*2^16
1042 #if 0 /* LoCosto version */
1043 l1s.pw_mgr.c_clk_init_max =(UWORD32)((UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1044 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))*
1045 65536)/LF_500PPM);//omaps00090550
1046 #else /* TSM30 version */
1047 l1s.pw_mgr.c_clk_init_max =(UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1048 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))*
1049 65536)/LF_500PPM;
1050 #endif
1051 // remember hf is expressed in nbr of clock in hz (ex 65Mhz,104Mhz)
1052 l1s.pw_mgr.c_delta_hf_acquis =(UWORD32) (((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_50PPM))*(l1_config.dpll*MCUCLK));//omaps00090550
1053 l1s.pw_mgr.c_delta_hf_update =(UWORD32)( ((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_6PPM ))*(l1_config.dpll*MCUCLK));//omaps00090550
1054 #endif
1055
1056 } /* l1_pwr_mgt_init() */
1057
1058 /*-------------------------------------------------------*/
1059 /* l1_initialize_var() */
1060 /*-------------------------------------------------------*/
1061 /* Parameters : */
1062 /* ------------- */
1063 /* Return : */
1064 /* ------------- */
1065 /* Description : */
1066 /* ------------- */
1067 /* This routine is used to initialize the l1a, l1s and */
1068 /* l1a_l1s_com global structures. */
1069 /*-------------------------------------------------------*/
1070 void l1_initialize_var(void)
1071 {
1072 UWORD32 i;
1073 UWORD8 task_id;
1074
1075 //++++++++++++++++++++++++++++++++++++++++++
1076 // Power management variables
1077 //++++++++++++++++++++++++++++++++++++++++++
1078 l1_pwr_mgt_init();
1079
1080 //++++++++++++++++++++++++++++++++++++++++++
1081 // Reset "l1s" structure.
1082 //++++++++++++++++++++++++++++++++++++++++++
1083
1084 // time counter used for debug and by L3 scenario...
1085 l1s.debug_time = 0;
1086
1087 // L1S tasks management...
1088 //-----------------------------------------
1089 for(task_id=0; task_id<NBR_DL_L1S_TASKS; task_id++)
1090 {
1091 if (!((task_id == ADC_CSMODE0) && (l1a_l1s_com.recovery_flag != FALSE)))
1092 {
1093 l1s.task_status[task_id].new_status = NOT_PENDING;
1094 l1s.task_status[task_id].current_status = INACTIVE;
1095 }
1096 }
1097 l1s.frame_count = 0;
1098 l1s.forbid_meas = 0;
1099 #if L1_GPRS
1100 #if 0 /* not present in TCS211 */
1101 l1s.tcr_prog_done=0;
1102 #endif
1103 #endif
1104 #if (AUDIO_DEBUG == 1)
1105 audio_reg_read_status=0;
1106 #endif
1107 // MFTAB management variables...
1108 //-----------------------------------------
1109 l1s.afrm = 0;
1110 l1s_clear_mftab(l1s.mftab.frmlst);
1111
1112 // Controle parameters... (miscellaneous)
1113 //-----------------------------------------
1114 #if (RF_FAM != 61)
1115 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>3); //F13.3 -> F16.0
1116 #endif
1117 #if (RF_FAM == 61)
1118 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>2); //F13.3 -> F14.0
1119 #endif
1120
1121
1122 l1s.afc_frame_count = 0;
1123
1124 #if (TOA_ALGO == 2)
1125 l1s.toa_var.toa_shift = ISH_INVALID;
1126 l1s.toa_var.toa_snr_mask = 0;
1127 l1s.toa_var.toa_frames_counter = 0;
1128 l1s.toa_var.toa_accumul_counter = 0;
1129 l1s.toa_var.toa_accumul_value = 0;
1130 l1s.toa_var.toa_update_fn = 0;
1131 l1s.toa_var.toa_update_flag = FALSE;
1132 #else
1133 l1s.toa_shift = ISH_INVALID;
1134 l1s.toa_snr_mask = 0;
1135 #if L1_GPRS
1136 l1s.toa_period_count = 0;
1137 l1s.toa_update = FALSE;
1138 #endif
1139 #endif
1140
1141 #if (L1_GPRS == 1)
1142 #if 0 /* not present in TCS211 */
1143 l1s.algo_change_synchro_active = FALSE;
1144 #endif
1145 #endif
1146
1147 #if (L1_RF_KBD_FIX == 1)
1148 l1s.total_kbd_on_time = 5000;
1149 l1s.correction_ratio = 1;
1150 #endif
1151 /* Initialising the repeated SACCH variables */
1152 #if (FF_REPEATED_SACCH == 1 )
1153 l1s.repeated_sacch.srr = 0;/* SACCH Repetiton Request */
1154 l1s.repeated_sacch.sro = 0;/* SACCH Repetiton Order */
1155 l1s.repeated_sacch.buffer_empty = TRUE;
1156 #endif /* FF_REPEATED_SACCH ==1*/
1157
1158 #if (FF_REPEATED_DL_FACCH == 1)
1159 l1s.repeated_facch.pipeline[0].buffer_empty=l1s.repeated_facch.pipeline[1].buffer_empty=TRUE;
1160 l1s.repeated_facch.counter_candidate=0;
1161 l1s.repeated_facch.counter=1;
1162 #endif/* (FF_REPEATED_DL_FACCH == 1) */
1163
1164 // Init the spurious_fb_detected flag
1165 l1s.spurious_fb_detected = FALSE;
1166
1167 // Flag registers for RF task controle...
1168 //-----------------------------------------
1169 l1s.tpu_ctrl_reg = 0;
1170 l1s.dsp_ctrl_reg = 0;
1171
1172 // Serving...
1173 //============
1174
1175 // Serving frame number management.
1176 //---------------------------------
1177 if (l1a_l1s_com.recovery_flag == FALSE)
1178 {
1179 l1s.actual_time.tc = 0;
1180 l1s.actual_time.fn = 0;
1181 l1s.actual_time.t1 = 0;
1182 l1s.actual_time.t2 = 0;
1183 l1s.actual_time.t3 = 0;
1184 l1s.actual_time.fn_in_report = 0;
1185 l1s.actual_time.fn_mod42432 = 0;
1186
1187 l1s.next_time.tc = 0;
1188 l1s.next_time.fn = 0;
1189 l1s.next_time.t1 = 0;
1190 l1s.next_time.t2 = 0;
1191 l1s.next_time.t3 = 0;
1192 l1s.next_time.fn_in_report = 0;
1193 l1s.next_time.fn_mod42432 = 0;
1194
1195 #if L1_GPRS
1196 l1s.actual_time.block_id = 0;
1197 l1s.next_time.block_id = 0;
1198 l1s.next_plus_time = l1s.next_time;
1199 l1s_increment_time(&(l1s.next_plus_time),1);
1200 l1s.ctrl_synch_before = FALSE;
1201 #if 0 /* not present in TCS211 */
1202 l1s.next_gauging_scheduled_for_PNP= 0;
1203 #endif
1204 #endif
1205 }
1206
1207 // TXPWR management.
1208 //-------------------
1209 l1s.reported_txpwr = 0;
1210 l1s.applied_txpwr = 0;
1211
1212 // Last RXQUAL value.
1213 //-------------------
1214 l1s.rxqual = 0;
1215
1216 // Hardware info.
1217 //---------------
1218 l1s.tpu_offset = 0;
1219 l1s.tpu_offset_hw = 0;
1220
1221 l1s.tpu_win = 0;
1222
1223 // Initialize TXPWR info.
1224 l1s.last_used_txpwr = NO_TXPWR;
1225
1226 #if (AMR == 1)
1227 // Reset DTX AMR status
1228 //---------------------
1229 l1s.dtx_amr_dl_on=FALSE;
1230 #endif
1231
1232 // Code version structure
1233 //-------------------------
1234
1235 // DSP versions & checksum
1236 l1s.version.dsp_code_version = 0;
1237 l1s.version.dsp_patch_version = 0;
1238 l1s.version.dsp_checksum = 0; // checksum patch+code DSP
1239
1240 l1s.version.mcu_tcs_program_release = PROGRAM_RELEASE_VERSION;
1241 l1s.version.mcu_tcs_internal = INTERNAL_VERSION;
1242 l1s.version.mcu_tcs_official = OFFICIAL_VERSION;
1243
1244 #if TESTMODE
1245 l1s.version.mcu_tm_version = TESTMODEVERSION;
1246 #else
1247 l1s.version.mcu_tm_version = 0;
1248 #endif
1249
1250 //++++++++++++++++++++++++++++++++++++++++++
1251 // Reset "l1a" structure.
1252 //++++++++++++++++++++++++++++++++++++++++++
1253
1254 // Downlink tasks management...
1255 // Uplink tasks management...
1256 // Measurement tasks management...
1257 //-----------------------------------------
1258
1259 if (l1a_l1s_com.recovery_flag == FALSE)
1260 {
1261 for(i=0; i<NBR_L1A_PROCESSES; i++)
1262 {
1263 l1a.l1a_en_meas[i] = 0;
1264 l1a.state[i] = 0; // RESET state.
1265 }
1266 }
1267 else
1268 {
1269 // L1A state for full list meas has to be maintained in case of recovery
1270 for(i=0; i<NBR_L1A_PROCESSES; i++)
1271 {
1272 if ((i != FULL_MEAS) && (i!= I_ADC))
1273 {
1274 l1a.l1a_en_meas[i] = 0;
1275 l1a.state[i] = 0; // RESET state.
1276 }
1277 }
1278 }
1279
1280 l1a.confirm_SignalCode = 0;
1281
1282 // Flag for forward/delete message management.
1283 //---------------------------------------------
1284 if (l1a_l1s_com.recovery_flag == FALSE)
1285 {
1286 l1a.l1_msg_forwarded = 0;
1287 }
1288
1289 #if (L1_VOCODER_IF_CHANGE == 1)
1290 // Reset new vocoder interface L1A global variables: automatic disabling and vocoder enabling flag.
1291 l1a.vocoder_state.automatic_disable = FALSE;
1292 l1a.vocoder_state.enabled = FALSE;
1293 #endif // if L1_VOCODER_IF_CHANGE == 1
1294 //++++++++++++++++++++++++++++++++++++++++++
1295 // Reset "l1a_l1s_com" structure.
1296 //++++++++++++++++++++++++++++++++++++++++++
1297
1298 l1a_l1s_com.l1a_activity_flag = TRUE;
1299 l1a_l1s_com.time_to_next_l1s_task = 0;
1300
1301 // Serving Cell...
1302 //=================
1303
1304 // Serving Cell identity and information.
1305 //---------------------------------------
1306 l1a_reset_cell_info(&(l1a_l1s_com.Scell_info));
1307
1308 l1a_l1s_com.Smeas_dedic.acc_sub = 0;
1309 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0;
1310 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0;
1311 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0;
1312 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0;
1313 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0;
1314 l1a_l1s_com.Smeas_dedic.dtx_used = 0;
1315
1316 #if REL99
1317 #if FF_EMR
1318 // Serving Cell identity EMR information.
1319 //---------------------------------------
1320 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0;
1321 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0;
1322 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0;
1323 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0;
1324 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0;
1325 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0;
1326 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0;
1327
1328 #endif
1329 #endif
1330
1331
1332 l1a_l1s_com.Scell_used_IL.input_level = l1_config.params.il_min;
1333 l1a_l1s_com.Scell_used_IL_d.input_level = l1_config.params.il_min;
1334 l1a_l1s_com.Scell_used_IL_dd.input_level = l1_config.params.il_min;
1335
1336 l1a_l1s_com.Scell_used_IL.lna_off = FALSE;
1337 l1a_l1s_com.Scell_used_IL_d.lna_off = FALSE;
1338 l1a_l1s_com.Scell_used_IL_dd.lna_off = FALSE;
1339
1340 // Synchro information.
1341 //---------------------------------------
1342 l1a_l1s_com.tn_difference = 0;
1343 l1a_l1s_com.dl_tn = 0;
1344 #if L1_FF_WA_OMAPS00099442
1345 l1a_l1s_com.change_tpu_offset_flag = FALSE;
1346 #endif
1347
1348 #if L1_GPRS
1349 l1a_l1s_com.dsp_scheduler_mode = GSM_SCHEDULER;
1350 #endif
1351
1352 // Idle parameters.
1353 //-----------------
1354 l1a_l1s_com.nbcchs.schedule_array_size=0;
1355 l1a_l1s_com.ebcchs.schedule_array_size=0;
1356 l1a_l1s_com.bcchn.current_list_size=0;
1357 l1a_l1s_com.nsync.current_list_size=0;
1358
1359 #if (GSM_IDLE_RAM != 0)
1360 l1s.gsm_idle_ram_ctl.l1s_full_exec = TRUE;
1361
1362 #if GSM_IDLE_RAM_DEBUG
1363 #if (CHIPSET == 10) && (OP_WCP == 1)
1364 l1s.gsm_idle_ram_ctl.TC_true_control=0;
1365 #endif // CHIPSET && OP_WCP
1366 #endif // GSM_IDLE_RAM_DEBUG
1367 #endif // GSM_IDLE_RAM
1368
1369 #if (L1_12NEIGH ==1)
1370 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1371 #else
1372 for (i=0;i<6;i++)
1373 #endif
1374 {
1375 l1a_l1s_com.nsync.list[i].status=NSYNC_FREE;
1376 }
1377 for (i=0;i<6;i++)
1378 {
1379 l1a_l1s_com.bcchn.list[i].status=NSYNC_FREE;
1380 }
1381
1382 // EOTD variables
1383 #if (L1_EOTD==1)
1384 l1a_l1s_com.nsync.eotd_meas_session=FALSE;
1385 l1a_l1s_com.nsync.fn_sb_serv;
1386 l1a_l1s_com.nsync.ta_sb_serv;
1387 #endif
1388
1389 // CBCH parameters.
1390 // ----------------
1391 // nothing to reset.
1392
1393 // Random Access information.
1394 // ----------------------------
1395 // nothing to reset.
1396
1397 // ADC management
1398 //---------------
1399 if (l1a_l1s_com.recovery_flag == FALSE)
1400 l1a_l1s_com.adc_mode = ADC_DISABLED;
1401
1402 // TXPWR management.
1403 //-------------------
1404 #if(L1_FF_MULTIBAND == 0)
1405 l1a_l1s_com.powerclass_band1 = 0;
1406 l1a_l1s_com.powerclass_band2 = 0;
1407 #else
1408 for( i = 0; i< (NB_MAX_SUPPORTED_BANDS); i++)
1409 {
1410 l1a_l1s_com.powerclass[i] = 0;
1411 }
1412 #endif
1413
1414 // Dedicated parameters.
1415 //----------------------
1416 l1a_l1s_com.dedic_set.aset = NULL;
1417 l1a_l1s_com.dedic_set.fset = NULL;
1418 l1a_l1s_com.dedic_set.SignalCode = 0;
1419 l1a_l1s_com.dedic_set.sync_tch = 0;
1420 l1a_l1s_com.dedic_set.reset_facch = FALSE;
1421 l1a_l1s_com.dedic_set.stop_tch = 0;
1422 #if (FF_L1_TCH_VOCODER_CONTROL)
1423 l1a_l1s_com.dedic_set.reset_sacch = FALSE;
1424 #if (L1_VOCODER_IF_CHANGE == 0)
1425 l1a_l1s_com.dedic_set.vocoder_on = TRUE;
1426 #if (W_A_DSP_PR20037 == 1)
1427 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
1428 #else // W_A_DSP_PR20037 == 0
1429 l1a_l1s_com.dedic_set.start_vocoder = FALSE;
1430 #endif // W_A_DSP_PR20037
1431 #else // L1_VOCODER_IF_CHANGE
1432 l1a_l1s_com.dedic_set.vocoder_on = FALSE;
1433 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_RESET_COMMAND;
1434 #endif // L1_VOCODER_IF_CHANGE
1435 #endif // FF_L1_TCH_VOCODER_CONTROL
1436
1437 l1a_l1s_com.dedic_set.radio_freq = 0;
1438 l1a_l1s_com.dedic_set.radio_freq_d = 0;
1439 l1a_l1s_com.dedic_set.radio_freq_dd = 0;
1440 #if ((REL99 == 1) && (FF_BHO == 1))
1441 // blind handover params in dedic set
1442 // Initialize the handover type to default value that is Normal Handover.
1443 l1a_l1s_com.dedic_set.handover_type = 0;
1444 l1a_l1s_com.dedic_set.long_rem_handover_type = 0;
1445 l1a_l1s_com.dedic_set.bcch_carrier_of_nbr_cell = 0;
1446 l1a_l1s_com.dedic_set.fn_offset = 0;
1447 l1a_l1s_com.dedic_set.time_alignment = 0;
1448 #endif
1449
1450 #if (L1_12NEIGH ==1)
1451 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1452 #else
1453 for (i=0;i<6;i++)
1454 #endif
1455 {
1456 l1a_l1s_com.nsync.list[i].sb26_offset = 0;
1457 }
1458
1459 l1a_l1s_com.dedic_set.pwrc = 0;
1460 l1a_l1s_com.dedic_set.handover_fail_mode = FALSE;
1461 #if (AMR == 1)
1462 l1a_l1s_com.dedic_set.sync_amr = FALSE;
1463 #endif
1464
1465 // Handover parameters.
1466 //---------------------
1467 // nothing to reset.
1468
1469 // Neighbour Cells...
1470 //====================
1471
1472 // FULL list.
1473 //-----------
1474 l1a_reset_full_list();
1475
1476 // BA list.
1477 //---------
1478 l1a_reset_ba_list();
1479 l1a_l1s_com.ba_list.new_list_present = FALSE;
1480
1481 #if L1_GPRS
1482 // Packet measurement: Reset of the frequency list.
1483 //-------------------------------------------------
1484 l1pa_reset_cr_freq_list();
1485 #endif
1486
1487 // L1S scheduler...
1488 //====================
1489
1490 // L1S tasks management...
1491 //-----------------------------------------
1492 {
1493 UWORD8 mem;
1494 mem = l1a_l1s_com.l1s_en_task[ADC_CSMODE0];
1495
1496 for(i=0; i<NBR_DL_L1S_TASKS; i++)
1497 {
1498 l1a_l1s_com.task_param[i] = SEMAPHORE_RESET;
1499 l1a_l1s_com.l1s_en_task[i] = TASK_DISABLED;
1500 }
1501
1502 // in case of recovery do not change the ADC initialization
1503 if (l1a_l1s_com.recovery_flag != FALSE)
1504 l1a_l1s_com.l1s_en_task[ADC_CSMODE0] = mem;
1505 }
1506
1507 // Measurement tasks management...
1508 //-----------------------------------------
1509 l1a_l1s_com.meas_param = 0;
1510 l1a_l1s_com.l1s_en_meas = 0;
1511
1512 // L1 mode...
1513 //-----------------------------------------
1514 if (l1a_l1s_com.recovery_flag == FALSE) // do not restart from CS_MODE0 after a recovery
1515 l1a_l1s_com.mode = CS_MODE0;
1516
1517 // Control algo variables.
1518 //-----------------------------------------
1519 l1a_l1s_com.fb_mode = 0;
1520 l1a_l1s_com.toa_reset = FALSE;
1521
1522 #if(L1_FF_MULTIBAND == 0)
1523 for(i=0; i<=l1_config.std.nbmax_carrier; i++)
1524 #else
1525 for(i=0; i<= NBMAX_CARRIER; i++)
1526 #endif
1527 {
1528 l1a_l1s_com.last_input_level[i].input_level = l1_config.params.il_min;
1529 l1a_l1s_com.last_input_level[i].lna_off = FALSE;
1530 }
1531
1532 #if FF_L1_IT_DSP_DTX
1533 // Fast DTX variables.
1534 //-----------------------------------------
1535 // Clear DTX interrupt condition
1536 l1a_apihisr_com.dtx.pending = FALSE;
1537 // Enable TX activity
1538 l1a_apihisr_com.dtx.tx_active = TRUE;
1539 // No DTX status awaited
1540 l1a_apihisr_com.dtx.dtx_status = DTX_AVAILABLE;
1541 // Fast DTX service latency timer
1542 l1a_apihisr_com.dtx.fast_dtx_ready_timer = 0;
1543 // Fast DTX service available
1544 l1a_apihisr_com.dtx.fast_dtx_ready = FALSE;
1545 #endif
1546 #if L1_RECOVERY
1547 l1s.recovery.frame_count = 0;
1548 #endif
1549
1550 #if (AUDIO_TASK == 1)
1551 l1audio_initialize_var();
1552 #endif
1553
1554 #if (L1_GTT == 1)
1555 l1gtt_initialize_var();
1556 #endif
1557
1558 #if (L1_MP3 == 1)
1559 l1mp3_initialize_var();
1560 #endif
1561
1562 #if (L1_MIDI == 1)
1563 l1midi_initialize_var();
1564 #endif
1565 //ADDED FOR AAC
1566 #if (L1_AAC == 1)
1567 l1aac_initialize_var();
1568 #endif
1569 #if (L1_DYN_DSP_DWNLD == 1)
1570 l1_dyn_dwnld_initialize_var();
1571 #endif
1572 #if (FF_L1_FAST_DECODING == 1)
1573 l1a_apihisr_com.fast_decoding.pending = FALSE;
1574 l1a_apihisr_com.fast_decoding.crc_error = FALSE;
1575 l1a_apihisr_com.fast_decoding.status = 0;
1576 l1a_apihisr_com.fast_decoding.deferred_control_req = FALSE;
1577 l1a_apihisr_com.fast_decoding.task = 0;
1578 l1a_apihisr_com.fast_decoding.burst_id = 0;
1579 l1a_apihisr_com.fast_decoding.contiguous_decoding = FALSE;
1580 #endif /* FF_L1_FAST_DECODING */
1581
1582
1583 #if(L1_CHECK_COMPATIBLE == 1)
1584 l1a.vcr_wait = FALSE;
1585 l1a.stop_req = FALSE;
1586 l1a.vcr_msg_param = TRUE;
1587 l1a.vch_auto_disable = FALSE;
1588
1589 #endif
1590
1591
1592 }
1593
1594
1595 /*---------------------------------------------------------*/
1596 /* l1_dpll_init_var() */
1597 /*---------------------------------------------------------*/
1598 /* Parameters : None */
1599 /* Return : None */
1600 /* Functionality : Initialize L1 DPLL variable for gauging */
1601 /* processing */
1602 /*---------------------------------------------------------*/
1603 void l1_dpll_init_var(void) {
1604
1605 #if (CODE_VERSION != SIMULATION)
1606 // Init DPLL variable
1607 //===================
1608 #if (CHIPSET == 2 || CHIPSET == 3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9)
1609 l1_config.dpll=PLL;
1610 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1611 {
1612 UWORD16 dpll_div;
1613 UWORD16 dpll_mul;
1614 #if (CHIPSET == 12)
1615 // not required for Locosto: There is NO CNTL_CLK_DSP in Locosto
1616 double dsp_div = CLKM_GET_DSP_DIV_VALUE;
1617 #endif
1618
1619 dpll_div=DPLL_READ_DPLL_DIV;
1620 dpll_mul=DPLL_READ_DPLL_MUL;
1621
1622 #if (CHIPSET == 12)
1623 // Not required for locsto due to the reason mentioned above.
1624 l1_config.dpll= ((double)(dpll_mul)/(double)(dpll_div+1))/(double)(dsp_div);
1625 #else
1626 l1_config.dpll= (double)(dpll_mul)/(double)(dpll_div+1);
1627 #endif
1628 }
1629 #endif
1630 #endif
1631
1632 } /* l1_dpll_init_var() */
1633
1634 /*-------------------------------------------------------------*/
1635 /* FUNCTION: l1_drp_wrapper_init */
1636
1637 /*-------------------------------------------------------------*/
1638
1639 #if(RF_FAM == 61)
1640 void l1_drp_wrapper_init (void)
1641 {
1642 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
1643 }
1644 #endif
1645
1646 /*-------------------------------------------------------------*/
1647 /* FUNCTION: l1_drp_init */
1648 /* Params: Void */
1649 /*
1650 Functionality: This function does the following
1651 1. Initialize Misc variables wrt DRP
1652 2a Copy the RAMP Tables into the DSP MCU API
1653 2b. Initialize other APIs wrt DCO
1654 3. Download Reference Software
1655 4. Call the function to : Start the REG_ON Script in the DRP
1656 */
1657 /*-------------------------------------------------------------*/
1658
1659 #if (L1_DRP == 1)
1660 #if (DRP_FW_EXT==1)
1661 #pragma DATA_SECTION(l1_drp_int_mem, ".drp_ptr")
1662 void * l1_drp_int_mem;
1663 #pragma DATA_SECTION(l1_drp_ext_mem, ".drp_ptr")
1664 void *l1_drp_ext_mem;
1665 #endif
1666 void l1_drp_init()
1667 {
1668 //int i;- OMAPS90550-new
1669 #if (DRP_FW_EXT==1)
1670 uint32 size_int=0;
1671 uint32 size_ext=0;
1672 #endif
1673 #if (RF_FAM == 61)
1674 volatile UWORD16 *ptr_drp_init16;
1675 UWORD16 drp_maj_version;
1676 UWORD16 drp_min_version;
1677
1678 //Initialize the following SRM_API, REG related address drp_srm_data = DRP_SRM_DATA_ADD,
1679 //drp_regs = DRP_REGS_BASE_ADD;, drp_srm_api = DRP_SRM_API_ADD
1680
1681 drp_api_addr_init();
1682
1683 #if (DRP_FW_EXT==1)
1684 drp_maj_version = (drp_ref_sw_ver >> 8) & 0xFF;
1685 drp_min_version = (drp_ref_sw_ver & 0xFF);
1686 #endif
1687
1688 //Initialize the following variables... TBD Danny
1689 //SRM_CW = 0x00000040, IRQ_CNT= 0x00000040 , TX_PTR_START_END_ADDR = 0X00200025,
1690 //RX_PTR_START_END_ADDR = 0X0000001F , 0XFFFE0806= 16
1691 //The registers are 32 bit since its a RHEA peripheral has to be writtin in 16 bit writes
1692 // This is done by the DRP script download
1693
1694 // The counter for # of DRP_DBB_RX_IRQs (in the wrapper) to be masked
1695 ptr_drp_init16 = (UWORD16 *) (DRP_DBB_RX_IRQ_MASK);
1696 (*ptr_drp_init16) = DRP_DBB_RX_IRQ_COUNT;
1697
1698 #endif //RF_FAM == 61
1699 l1s.boot_result=0;
1700 #if (DRP_FW_EXT==1)
1701 if(!((drp_min_version >= L1_DRP_COMPAT_MINOR_VER) && (drp_maj_version == L1_DRP_COMPAT_MAJOR_VER))) {
1702 l1s.boot_result = 1;
1703 return;
1704 }
1705 drp_get_memory_size(&size_int,&size_ext);
1706 /* FIXME FIXME ERROR handling for memory allocation failure */
1707 if(size_int)
1708 {
1709 l1_drp_int_mem=os_alloc_sig(size_int);
1710 if(l1_drp_int_mem==NULL)
1711 {
1712 /*FIXME Error Handling Here */
1713 l1s.boot_result = 1;
1714 return;
1715 }
1716 }
1717 if(size_ext)
1718 {
1719 l1_drp_ext_mem=os_alloc_sig(size_ext);
1720
1721 if(l1_drp_ext_mem==NULL)
1722 {
1723 /*FIXME Error Handling Here */
1724 l1s.boot_result = 1;
1725 return;
1726 }
1727 }
1728
1729 // Populate pointers
1730 if(drpfw_init(&modem_func_jump_table,&modem_var_jump_table))
1731 {
1732 // This condition should not be reached in phase 1 of DRP FW
1733 // Extraction. DRP and L1 software should always be compatible
1734 l1s.boot_result = 1;
1735 return;
1736 }
1737
1738 ((T_DRP_ENV_INT_BLK *)l1_drp_int_mem)->g_pcb_config = RF_BAND_SYSTEM_INDEX; //OMAPS148175
1739
1740 #endif // DRP_FW_EXT==1
1741 // This function would takes care of drp_ref_sw download till that is in place this would be a dummy function
1742 // Testing PLD_WriteRegister(0x0440, 0x165c);
1743 #if (RF_FAM == 60) // PLD board
1744 // for PLD board script downloading will happen through USP driver
1745 // load ref_sw_main
1746 // drp_ref_sw_upload(drp_ref_sw);
1747 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1748 #elif (RF_FAM == 61) // Locosto based board
1749 // load ref_sw_main
1750 // drp_ref_sw_upload(drp_ref_sw); // TBD replace with DRP Copy function...
1751 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1752 #endif
1753
1754 #if (L1_DRP_DITHERING == 1)
1755 (*(volatile UINT8 *)CONF_MUX_VIEW8) = 0x01;
1756 (*(volatile UINT8 *)CONF_DEBUG_SEL_TST_8) = 0x07;
1757 (*(volatile UINT8 *)CONF_GPIO_17) = 0x02;
1758 (*(volatile UINT8 *)CONF_LOCOSTO_DEBUG) = 0x00;
1759 #endif
1760
1761 }
1762 #endif // L1_DRP
1763
1764 /*-------------------------------------------------------*/
1765 /* l1_initialize() */
1766 /*-------------------------------------------------------*/
1767 /* Parameters : */
1768 /* Return : */
1769 /* Functionality : */
1770 /*-------------------------------------------------------*/
1771 void l1_initialize(T_MMI_L1_CONFIG *mmi_l1_config)
1772 {
1773 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) || (TRACE_TYPE == 5)
1774 l1_trace_init();
1775 #endif
1776
1777 // this is not a recovery initialization .
1778 l1a_l1s_com.recovery_flag = FALSE;
1779
1780 // initialize the ratio of the wait loop
1781 // must be initialized before using the wait_ARM_cycles() function !!!
1782 #if (CODE_VERSION != SIMULATION)
1783 initialize_wait_loop();
1784 #endif
1785
1786 // Init Layer 1 configuration
1787 //===========================
1788 #if(L1_FF_MULTIBAND == 0)
1789 l1_config.std.id = mmi_l1_config->std;
1790 #endif
1791
1792 l1_config.tx_pwr_code = mmi_l1_config->tx_pwr_code;
1793 #if 0 /* not present in TCS211 */
1794 #if IDS
1795 l1_config.ids_enable = mmi_l1_config->ids_enable;
1796 #endif
1797 l1_config.facch_test.enable = mmi_l1_config->facch_test.enable;
1798 l1_config.facch_test.period = mmi_l1_config->facch_test.period;
1799 #endif
1800 l1_config.dwnld = mmi_l1_config->dwnld;
1801
1802 #if TESTMODE
1803 // Initialize TestMode params: must be done after Omega power-on
1804 l1_config.TestMode = FALSE;
1805 // Enable control algos and ADC
1806 l1_config.agc_enable = 1;
1807 l1_config.afc_enable = 1;
1808 l1_config.adc_enable = 1;
1809 #if (FF_REPEATED_SACCH == 1)
1810 l1_config.repeat_sacch_enable = 1; /* Repeated SACCH mode enabled */
1811 #endif /* (FF_REPEATED_SACCH == 1) */
1812 #if (FF_REPEATED_DL_FACCH == 1)
1813 l1_config.repeat_facch_dl_enable = 1; /* Repeated SACCH mode enabled */
1814 #endif /* ( FF_REPEATED_DL_FACCH == 1) */
1815 #endif
1816
1817 // sleep management configuration
1818 //===============================
1819 l1s.pw_mgr.mode_authorized = mmi_l1_config->pwr_mngt_mode_authorized;
1820 l1s.pw_mgr.clocks = mmi_l1_config->pwr_mngt_clocks;
1821 l1_config.pwr_mngt = mmi_l1_config->pwr_mngt;
1822
1823 Cust_init_std();
1824 Cust_init_params();
1825
1826
1827
1828 // Init DPLL variable
1829 //===================
1830 l1_dpll_init_var();
1831
1832 // Reset hardware (DSP,Analog Baseband device , TPU) ....
1833 //========================================================
1834 #if (CODE_VERSION != SIMULATION)
1835 dsp_power_on();
1836 l1_abb_power_on();
1837 #if (L1_DRP == 1)
1838 l1_drp_init();
1839 //required for interworking with Isample 2.1 and Isample 2.5
1840 #if (DRP_FW_EXT == 1)
1841 if (!l1s.boot_result)
1842 {
1843 #endif
1844 //for DRP Calibration
1845 Cust_init_params_drp();
1846 drp_efuse_init();
1847 #if (DRP_FW_EXT == 1)
1848 } /* end if boot_result != 0 */
1849 #endif
1850
1851 #endif
1852
1853 #endif
1854
1855 // Initialize hardware....(DSP, TPU)....
1856 //=================================================
1857 l1_tpu_init();
1858 l1_dsp_init();
1859
1860 // Initialize L1 variables (l1a, l1s, l1a_l1s_com).
1861 //=================================================
1862 l1_initialize_var();
1863
1864 // API check function
1865 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38) || (DSP == 39)) && (CODE_VERSION != SIMULATION))
1866 l1_api_dump();
1867 #endif
1868
1869 #if (L1_GPRS)
1870 // Initialize L1 variables used in packet mode (l1pa, l1ps, l1pa_l1ps_com).
1871 //========================================================================
1872 initialize_l1pvar();
1873 #endif
1874
1875 // Initialize statistics mode.......
1876 //=================================================
1877 #if TRACE_TYPE==3
1878 reset_stats();
1879 #endif
1880 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
1881 Cust_navc_ctrl_status(1);//start - NAVC
1882 #endif//end of (OP_L1_STANDALONE == 1 || L1_NAVC == 1 )
1883
1884 }
1885
1886 /*-------------------------------------------------------*/
1887 /* l1_initialize_for_recovery */
1888 /*-------------------------------------------------------*/
1889 /* Parameters : */
1890 /* Return : */
1891 /* Functionality : This function is called for L1 */
1892 /* recovery after a Crash. When there are 100 COM error */
1893 /* or if ther are 100 PM =0 from the DSP Successively. */
1894 /* The Layer 1 Crashes. The next time the Protocol stack */
1895 /* requests for Full Rx Measurement (viz Cell selection) */
1896 /* This function gets called and the L1 recovery is */
1897 /* initiated. */
1898 /*-------------------------------------------------------*/
1899 #if L1_RECOVERY
1900 void l1_initialize_for_recovery(void)
1901 {
1902 LA_ResetLead(); // set DSP in reset mode
1903 initialize_wait_loop();
1904
1905 dsp_power_on(); // the reset mode is disabled here
1906 l1_abb_power_on();
1907 #if (L1_DRP == 1)
1908 l1_drp_init();
1909 //Required for interworking with Isample 2.1 and Isample 2.5
1910 Cust_init_params_drp();
1911 drp_efuse_init();
1912 #endif
1913 l1_tpu_init();
1914 #if 0 /* not in TCS211 */
1915 wait_ARM_cycles(convert_nanosec_to_cycles(11000000)); // wait of 5.5 msec
1916 #endif
1917 l1_dsp_init();
1918 l1_initialize_var();
1919
1920 #if L1_GPRS
1921 initialize_l1pvar();
1922 #endif
1923
1924 l1a_l1s_com.recovery_flag = FALSE;
1925
1926 // clear pending IQ_FRAME it and enable it
1927 #if (CHIPSET >= 4 )
1928 #if (CHIPSET == 12) || (CHIPSET == 15)
1929 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1930 #else
1931 * (volatile UWORD16 *) INTH_IT_REG1 &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1932 #endif
1933 #else
1934 * (volatile UWORD16 *) INTH_IT_REG &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1935 #endif
1936
1937 }
1938 #endif