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comparison src/cs/layer1/cfile/l1_drive.c @ 0:4e78acac3d88

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src/{condat,cs,gpf,nucleus}: import from Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 16 Oct 2020 06:23:26 +0000
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-1:000000000000 0:4e78acac3d88
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_DRIVE.C
4 *
5 * Filename l1_drive.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_DRIVE_C
11
12 #include "l1_confg.h"
13
14 #if (RF_FAM == 61)
15 #include "apc.h"
16 #endif
17
18 #define W_A_DSP_PR20037 1 /* FreeCalypso */
19
20 #if ((L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)&&(W_A_DSP_PR20037 == 1))
21 #include "nucleus.h"
22 #endif
23 #include "l1_macro.h"
24 #if (CODE_VERSION == SIMULATION)
25 #include <string.h>
26 #include "l1_types.h"
27 #include "sys_types.h"
28 #include "l1_const.h"
29 #include "l1_time.h"
30 #if TESTMODE
31 #include "l1tm_defty.h"
32 #endif
33 #if (AUDIO_TASK == 1)
34 #include "l1audio_const.h"
35 #include "l1audio_cust.h"
36 #include "l1audio_defty.h"
37 #endif
38 #if (L1_GTT == 1)
39 #include "l1gtt_const.h"
40 #include "l1gtt_defty.h"
41 #endif
42 #if (L1_MP3 == 1)
43 #include "l1mp3_defty.h"
44 #endif
45 #if (L1_MIDI == 1)
46 #include "l1midi_defty.h"
47 #endif
48 //ADDED FOR AAC
49 #if (L1_AAC == 1)
50 #include "l1aac_defty.h"
51 #endif
52 #include "l1_defty.h"
53 #include "l1_varex.h"
54 #include "cust_os.h"
55 #include "l1_msgty.h"
56 #if TESTMODE
57 #include "l1tm_varex.h"
58 #endif
59 #if L2_L3_SIMUL
60 #include "hw_debug.h"
61 #endif
62
63 #if L1_GPRS
64 #include "l1p_cons.h"
65 #include "l1p_msgt.h"
66 #include "l1p_deft.h"
67 #include "l1p_vare.h"
68 #include "l1p_sign.h"
69 #endif
70
71 #include <stdio.h>
72 #include "sim_cfg.h"
73 #include "sim_cons.h"
74 #include "sim_def.h"
75 #include "sim_var.h"
76
77 #include "l1_ctl.h"
78
79 #else
80
81 #include <string.h>
82 #include "l1_types.h"
83 #include "sys_types.h"
84 #include "l1_const.h"
85 #include "l1_time.h"
86 #if TESTMODE
87 #include "l1tm_defty.h"
88 #endif
89 #if (AUDIO_TASK == 1)
90 #include "l1audio_const.h"
91 #include "l1audio_cust.h"
92 #include "l1audio_defty.h"
93 #endif
94 #if (L1_GTT == 1)
95 #include "l1gtt_const.h"
96 #include "l1gtt_defty.h"
97 #endif
98 #if (L1_MP3 == 1)
99 #include "l1mp3_defty.h"
100 #endif
101 #if (L1_MIDI == 1)
102 #include "l1midi_defty.h"
103 #endif
104 //ADDED FOR AAC
105 #if (L1_AAC == 1)
106 #include "l1aac_defty.h"
107 #endif
108 #include "l1_defty.h"
109 #include "l1_varex.h"
110 #include "cust_os.h"
111 #include "l1_msgty.h"
112 #if TESTMODE
113 #include "l1tm_varex.h"
114 #endif
115 #if L2_L3_SIMUL
116 #include "hw_debug.h"
117 #endif
118 #include "tpudrv.h"
119
120 #if L1_GPRS
121 #include "l1p_cons.h"
122 #include "l1p_msgt.h"
123 #include "l1p_deft.h"
124 #include "l1p_vare.h"
125 #include "l1p_sign.h"
126 #endif
127
128 #include "l1_ctl.h"
129
130 #endif
131
132 #if (RF_FAM == 61)
133 #include "tpudrv61.h"
134 #endif
135
136
137
138 /*
139 * Prototypes of external functions used in this file.
140 *
141 * FreeCalypso change: removed all those prototypes which appear
142 * in tpudrv.h, and kept only the additional ones.
143 */
144
145 #if ((REL99 == 1) && (FF_BHO == 1))
146 #if (L1_MADC_ON == 1)
147 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq,UWORD8 adc_active);
148 #else
149 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq);
150 #endif
151 #endif//#if ((REL99 == 1) && (FF_BHO == 1))
152
153 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq);
154 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
155 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq
156 #if(REL99 && FF_PRF)
157 ,UWORD8 number_uplink_timeslot
158 #endif
159 );
160 #endif
161
162 #if L1_GPRS
163 void l1ps_reset_db_mcu_to_dsp(T_DB_MCU_TO_DSP_GPRS *page_ptr);
164 #endif
165
166 /*-------------------------------------------------------*/
167 /* l1ddsp_load_info() */
168 /*-------------------------------------------------------*/
169 /* Parameters : */
170 /* Return : */
171 /* Functionality : */
172 /*-------------------------------------------------------*/
173 void l1ddsp_load_info(UWORD32 task, API *info_ptr, UWORD8 *data)
174 {
175 if(task == RACH_DSP_TASK)
176 // RACH info. format is only 2 words...
177 {
178 info_ptr[0] = ((API)(data[0])) | ((API)(data[1])<<8);
179 }
180 else
181 // Fill mcu-dsp comm. buffer.
182 {
183 UWORD8 i,j;
184
185 // Fill data block Header...
186 info_ptr[0] = (1 << B_BLUD); // 1st word: Set B_BLU bit.
187 info_ptr[1] = 0; // 2nd word: cleared.
188 info_ptr[2] = 0; // 3rd word: cleared.
189
190 if((info_ptr == l1s_dsp_com.dsp_ndb_ptr->a_du_0) ||
191 (info_ptr == l1s_dsp_com.dsp_ndb_ptr->a_du_1))
192 // DATA traffic buffers: size of buffer is 260 bit -> 17 words but DATA traffic uses
193 // only a max of 240 bit (30 bytes) -> 15 words.
194 {
195 for (i=0, j=(3+0); j<(3+15); j++)
196 {
197 info_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8);
198 i += 2;
199 }
200 #if (TRACE_TYPE==3)
201 if (l1_stats.type == PLAY_UL)
202 {
203 for (i=0, j=(3+0); j<(3+17); j++)
204 {
205 info_ptr[j] = ((API)(data[i])) |
206 ((API)(data[i]) << 8);
207 i ++;
208 }
209 }
210 #endif
211 }
212 else
213 // Data block for control purpose is 184 bit length: 23 bytes: 12 words (16 bit/word).
214 {
215 // Copy first 22 bytes in the first 11 words after header.
216 for (i=0, j=(3+0); j<(3+11); j++)
217 {
218 info_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8);
219 i += 2;
220 }
221
222 // Copy last UWORD8 (23rd) in the 12th word after header.
223 info_ptr[14] = data[22];
224 }
225 }
226 }
227
228 /*-------------------------------------------------------*/
229 /* l1ddsp_load_monit_task() */
230 /*-------------------------------------------------------*/
231 /* Parameters : */
232 /* Return : */
233 /* Functionality : */
234 /*-------------------------------------------------------*/
235 void l1ddsp_load_monit_task(API monit_task, API fb_mode)
236 {
237 l1s_dsp_com.dsp_db_w_ptr->d_task_md = monit_task; // Write number of measurements
238
239 if(l1a_l1s_com.mode == CS_MODE)
240 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = fb_mode; // Write FB detection algo. mode.
241 else
242 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = 1;
243 }
244
245
246 /* --------------------------------------------------- */
247
248 /* Locosto Changes....*/
249
250 // Parameters: UWORD16 afcval
251 // Return :Void
252 //Functionality: TPU to accept the afcvalue from the MCU and copy it
253 //to the mem_xtal before triggering of AFC Script in DRP
254
255 #if(RF_FAM == 61)
256 void l1dtpu_load_afc(UWORD16 afc)
257 {
258 l1dmacro_afc(afc, 0);
259 }
260
261 /* --------------------------------------------------- */
262
263 /* Locosto Changes....*/
264
265 /* Parameters: API dco_algo_ctl_sb */
266 /* Functionality: Loads the API d_dco_ctl_algo_sb in the API
267 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
268
269 /* --------------------------------------------------- */
270
271 void l1ddsp_load_dco_ctl_algo_sb (UWORD16 dco_ctl_algo)
272 {
273 #if (DSP == 38) || (DSP == 39)
274 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_sb = (API) dco_ctl_algo;
275 #endif
276 }
277
278 /* --------------------------------------------------- */
279
280 /* Locosto Changes....*/
281
282 /* Parameters: API dco_algo_ctl_nb */
283 /* Functionality: Loads the API d_dco_ctl_algo_nb in the API
284 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
285
286 /* --------------------------------------------------- */
287
288 void l1ddsp_load_dco_ctl_algo_nb (UWORD16 dco_ctl_algo)
289 {
290 #if (DSP == 38) || (DSP == 39)
291 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_nb = (API) dco_ctl_algo;
292 #endif
293
294 }
295 /* --------------------------------------------------- */
296
297 /* Locosto Changes....*/
298
299 /* Parameters: API dco_algo_ctl_pw */
300 /* Functionality: Loads the API d_dco_ctl_algo_pw in the API
301 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
302
303 /* --------------------------------------------------- */
304
305 void l1ddsp_load_dco_ctl_algo_pw (UWORD16 dco_ctl_algo)
306 {
307 #if (DSP == 38) || (DSP == 39)
308 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_pw = (API) dco_ctl_algo;
309 #endif
310 }
311
312 #endif
313
314 /*-------------------------------------------------------*/
315 /* l1ddsp_load_afc() */
316 /*-------------------------------------------------------*/
317 /* Parameters : */
318 /* Return : */
319 /* Functionality : */
320 /*-------------------------------------------------------*/
321 void l1ddsp_load_afc(API afc)
322 {
323 #if (L1_EOTD==1)
324 // NEW !!! For EOTD measurements in IDLE mode only, cut AFC updates....
325 #if (L1_GPRS)
326 if ( (l1a_l1s_com.nsync.eotd_meas_session == FALSE) ||
327 (l1a_l1s_com.mode == DEDIC_MODE)||
328 (l1a_l1s_com.l1s_en_task[PDTCH] == TASK_ENABLED))
329 #else
330 if ( (l1a_l1s_com.nsync.eotd_meas_session == FALSE) ||
331 (l1a_l1s_com.mode == DEDIC_MODE))
332 #endif
333
334 {
335 #endif
336 //######################## For DSP Rom #################################
337 l1s_dsp_com.dsp_db_w_ptr->d_afc = afc; // Write new afc command.
338 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
339 // NOTE: In Locosto AFC loading is w.r.t DRP not in ABB
340 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= (1 << B_AFC); // Validate new afc value.
341 #endif
342 #if (L1_EOTD==1)
343 }
344 #endif
345
346 }
347
348 /*-------------------------------------------------------*/
349 /* l1ddsp_load_txpwr() */
350 /*-------------------------------------------------------*/
351 /* Parameters : */
352 /* Return : */
353 /* Functionality : */
354 /*Notes:
355
356 While Programming APC Ramp always Program the APCDEL also
357 Cal+:
358 APCDEL1: LSB Dwn(9:5):Up(4:0)
359 APCDEL2: MSB Dwn(9:5):Up(4:0)
360
361 Locosto:
362 APCDEL1: LSB Dwn(9:5):Up(4:0)
363 APCDEL2: MSB Dwn(9:5):Up(4:0)
364 -----
365 Cal+
366 APCRAM : Dwn(51:11)Up(10:6)Forced(0)
367 Locosto:
368 APCRAM: Dwn(9:5)Up(4:0)
369
370 For AFC, APCDEL1, APCDEL2, APCRAMP the Control word d_ctl_abb is checked
371 i f they are reqd to be updated.
372
373 For AUXAPC (Cal+), the last bit = 1 would mean the DSP would pick it at Tx
374 For APCLEV (Loc), it is picked at every Tx, for dummy burst DSP would make it 0
375 */
376
377 /*-------------------------------------------------------*/
378 void l1ddsp_load_txpwr(UWORD8 txpwr, UWORD16 radio_freq)
379 {
380 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
381 UWORD16 pwr_data;
382 #endif
383
384 //config
385 if (l1_config.tx_pwr_code ==0)
386 {
387 // Fixed TXPWR.
388 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = l1_config.params.fixed_txpwr; // GSM management disabled: Fixed TXPWR used.
389
390
391 #if(RF_FAM == 61)
392 //Locosto has new API for Ramp
393 #if (DSP == 38) || (DSP == 39)
394 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
395 #endif
396 #else
397 #if (CODE_VERSION != SIMULATION)
398 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/
399 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
400 #endif
401 #endif
402
403 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
404 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
405 #endif
406
407 #if(RF_FAM == 61)
408 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
409 #endif
410
411 }
412 else
413 {
414 static UWORD8 last_used_freq_band = 0;
415 UWORD8 freq_band;
416
417 #if (L1_FF_MULTIBAND == 0)
418 // Check whether band has changed
419 // This will be used to reload ramps
420 if ((l1_config.std.id == DUAL) ||
421 (l1_config.std.id == DUALEXT) ||
422 (l1_config.std.id == DUAL_US))
423 {
424 if (radio_freq < l1_config.std.first_radio_freq_band2)
425 freq_band = BAND1;
426 else
427 freq_band = BAND2;
428 }
429 else
430 freq_band = BAND1;
431 #else
432
433 freq_band = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq);
434
435 #endif
436
437 // Note: txpwr = NO_TXPWR is reserved for forcing the transmitter off
438 // ----- (to suppress SACCH during handover, for example)
439
440 /*** Check to see if the TXPWR is to be suppressed (txpwr = NO_TXPWR) ***/
441
442 if(txpwr == NO_TXPWR)
443 {
444 /*** No transmit ***/
445 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
446 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = 0x12; // AUXAPC initialization addr 9 pg 0 Omega
447 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
448 #endif
449
450 #if(RF_FAM == 61 ) //Locosto without Syren Format
451 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = (API) 0; // APCLEV
452 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
453 #endif
454
455 l1s.last_used_txpwr = NO_TXPWR;
456 return;
457 }
458 else
459 {
460 /*** Get power data according to clipped TXPWR ***/
461 pwr_data = Cust_get_pwr_data(txpwr, radio_freq
462 #if(REL99 && FF_PRF)
463 ,1
464 #endif
465 );
466
467 /*** Load power control level adding the APC address register ***/
468 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
469 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = ((pwr_data << 6) | 0x12);
470 // AUXAPC initialization addr 9 pg 0 Omega
471 #endif
472
473 #if(RF_FAM == 61)
474 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = (API)(pwr_data);
475 #endif
476 }
477
478 #if TESTMODE
479 #if(RF_FAM == 61)
480 // Currently for RF_FAM=61 Enabling APC-Ramp, APCDEL1 and APCDEL2 writing always i.e. in every TDMA frame
481 // TODO: Check whether this is okay
482 if ((l1_config.TestMode) && (l1_config.tmode.rf_params.down_up & TMODE_UPLINK))
483 #else
484 if ((l1_config.TestMode) && (l1_config.tmode.rf_params.down_up & TMODE_UPLINK) &&
485 ((l1s.last_used_txpwr != txpwr) || (l1_config.tmode.rf_params.reload_ramps_flag)))
486 #endif
487 {
488 #if(RF_FAM == 61)
489 #if (DSP == 38) || (DSP == 39)
490 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
491 #endif
492 #else
493 #if (CODE_VERSION != SIMULATION)
494 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
495 #endif
496 #endif
497
498 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
499 // Setting bit 3 of this register causes DSP to write to APCDEL1 register in Omega. However,
500 // we are controlling this register from MCU through the SPI. Therefore, set it to 0.
501 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (0 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
502 #endif
503
504 #if (RF_FAM == 61)
505 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
506 #endif
507
508 l1s.last_used_txpwr = txpwr;
509 l1_config.tmode.rf_params.reload_ramps_flag = 0;
510 }
511 else
512 #endif
513
514 if ((l1s.last_used_txpwr != txpwr) || (last_used_freq_band != freq_band))
515 {
516 /*** Power level or band has changed, so update the ramp, and trigger the data send to ABB ***/
517
518 l1s.last_used_txpwr = txpwr;
519 last_used_freq_band = freq_band;
520
521 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/
522 #if(RF_FAM == 61)
523 #if (DSP == 38) || (DSP == 39)
524 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
525 #endif
526 #else
527 #if (CODE_VERSION != SIMULATION)
528 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
529 #endif
530 #endif
531
532 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) ||(RF_FAM == 61))
533 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
534 #endif
535 }
536 }
537 }
538
539 #if (FF_L1_FAST_DECODING == 1)
540 /*-------------------------------------------------------*/
541 /* l1ddsp_load_fp_task() */
542 /*-------------------------------------------------------*/
543 /* Parameters : */
544 /* Return : */
545 /* Functionality : */
546 /*-------------------------------------------------------*/
547 void l1ddsp_load_fast_dec_task(API task, UWORD8 burst_id)
548 {
549 if (l1s_check_fast_decoding_authorized(task))
550 {
551 //l1s_dsp_com.dsp_db_w_ptr->d_fast_paging_ctrl = 0x0001
552 l1s_dsp_com.dsp_db_common_w_ptr->d_fast_paging_ctrl = 0x00001;
553 if(burst_id == BURST_1)
554 {
555 l1s_dsp_com.dsp_db_common_w_ptr->d_fast_paging_ctrl |= 0x8000;
556 }
557 }
558 }
559 #endif /* FF_L1_FAST_DECODING */
560
561 /*-------------------------------------------------------*/
562 /* l1ddsp_load_rx_task() */
563 /*-------------------------------------------------------*/
564 /* Parameters : */
565 /* Return : */
566 /* Functionality : */
567 /*-------------------------------------------------------*/
568 void l1ddsp_load_rx_task(API rx_task, UWORD8 burst_id, UWORD8 tsq)
569 {
570 l1s_dsp_com.dsp_db_w_ptr->d_task_d = rx_task; // Write RX task Identifier.
571 l1s_dsp_com.dsp_db_w_ptr->d_burst_d = burst_id; // Write RX burst Identifier.
572 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; // Write end of task DSP state.
573 }
574
575 /*-------------------------------------------------------*/
576 /* l1ddsp_load_tx_task() */
577 /*-------------------------------------------------------*/
578 /* Parameters : */
579 /* Return : */
580 /* Functionality : */
581 /*-------------------------------------------------------*/
582 void l1ddsp_load_tx_task(API tx_task, UWORD8 burst_id, UWORD8 tsq)
583 {
584 l1s_dsp_com.dsp_db_w_ptr->d_task_u = tx_task; // write TX task Identifier.
585 l1s_dsp_com.dsp_db_w_ptr->d_burst_u = burst_id; // write TX burst Identifier.
586 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; // Write end of task DSP state.
587 }
588
589 /*-------------------------------------------------------*/
590 /* l1ddsp_load_ra_task() */
591 /*-------------------------------------------------------*/
592 /* Parameters : */
593 /* Return : */
594 /* Functionality : */
595 /*-------------------------------------------------------*/
596 void l1ddsp_load_ra_task(API ra_task)
597 {
598 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = ra_task; // write RA task Identifier.
599 }
600
601 /*-------------------------------------------------------*/
602 /* l1ddsp_load_tch_mode() */
603 /*-------------------------------------------------------*/
604 /* Parameters : */
605 /* Return : */
606 /* Functionality : */
607 /*-------------------------------------------------------*/
608 void l1ddsp_load_tch_mode(UWORD8 dai_mode, BOOL dtx_allowed)
609 {
610 // TCH mode register.
611 // bit[0] -> b_eotd.
612 // bit[1] -> b_audio_async only for WCP
613 // bit [2] -> b_dtx.
614 // bit[3] -> play_ul when set to 1
615 // bit[4] -> play_dl when set to 1
616 // bit[5] -> DTX selection for voice memo
617 // bit[6] -> Reserved for ciphering debug
618 // bit[7..10] -> Reserved for ramp up control
619 // bit[11] -> Reserved for analog device selection
620
621 #if (DSP == 32)
622 UWORD16 mask = 0xfffb;
623 #else // NO OP_WCP
624 UWORD16 mask = 0xfff8;
625 #endif
626
627 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = (l1s_dsp_com.dsp_ndb_ptr->d_tch_mode & mask)
628 | (dtx_allowed<<2);
629 #if (L1_EOTD == 1)
630 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
631 #endif
632 }
633
634 #if (AMR == 1)
635 /*-------------------------------------------------------*/
636 /* l1ddsp_load_tch_param() */
637 /*-------------------------------------------------------*/
638 /* Parameters : */
639 /* Return : */
640 /* Functionality : */
641 /*-------------------------------------------------------*/
642 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
643 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
644 UWORD8 chan_type, UWORD8 subchannel,
645 UWORD8 tch_loop, UWORD8 sync_tch,
646 UWORD8 sync_amr,
647 UWORD8 reset_sacch,
648 #if !FF_L1_IT_DSP_DTX
649 UWORD8 vocoder_on)
650 #else
651 UWORD8 vocoder_on,
652 BOOL dtx_dsp_interrupt)
653 #endif
654 #else
655 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
656 UWORD8 chan_type, UWORD8 subchannel,
657 UWORD8 tch_loop, UWORD8 sync_tch,
658 #if !FF_L1_IT_DSP_DTX
659 UWORD8 sync_amr)
660 #else
661 UWORD8 sync_amr, BOOL dtx_dsp_interrupt)
662 #endif
663 #endif
664 {
665 UWORD32 count_0;
666 UWORD32 count_1;
667 UWORD32 d_ctrl_tch;
668 UWORD32 d_fn;
669
670 // d_ctrl_tch
671 // ----------
672 // bit [0..3] -> b_chan_mode
673 // bit [4..7] -> b_chan_type
674 // bit [8] -> b_sync_tch_ul
675 // bit [9] -> b_sync_amr
676 // bit [10] -> b_stop_tch_ul
677 // bit [11] -> b_stop_tch_dl
678 // bit [12..14] -> b_tch_loop
679 // bit [15] -> b_subchannel
680 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
681 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
682 (sync_tch<<B_SYNC_TCH_UL) | (sync_amr<<B_SYNC_AMR) |
683 (tch_loop<<B_TCH_LOOP) | (reset_sacch<<B_RESET_SACCH) | (vocoder_on<<B_VOCODER_ON);
684 #else
685 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
686 (sync_tch<<B_SYNC_TCH_UL) | (sync_amr<<B_SYNC_AMR) |
687 (tch_loop<<B_TCH_LOOP);
688 #endif
689
690 // d_fn
691 // ----
692 // bit [0..7] -> b_fn_report
693 // bit [8..15] -> b_fn_sid
694 d_fn = (next_time->fn_in_report) | ((next_time->fn%104)<<8);
695
696 // a_a5fn
697 // ------
698 // count_0 (a_a5fn[0]), bit [0..4] -> T2.
699 // count_0 (a_a5fn[1]), bit [5..10] -> T3.
700 // count_1 (a_a5fn[0]), bit [0..10] -> T1.
701 count_0 = ((UWORD16)next_time->t3 << 5) | (next_time->t2);
702 count_1 = (next_time->t1);
703
704 l1s_dsp_com.dsp_db_w_ptr->d_fn = d_fn; // write both Fn_sid, Fn_report.
705 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[0] = count_0; // cyphering FN part 1.
706 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[1] = count_1; // cyphering FN part 2.
707 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = d_ctrl_tch; // Channel config.
708 #if FF_L1_IT_DSP_DTX
709 // ### TBD: report this block below in the other instance of this function
710 // DTX interrupt request is latched by DSP in TDMA3 (TCH-AFS, TCH-AHS0) or TDMA0 (TCH-AHS1)
711 if ((chan_mode == TCH_AFS_MODE) || (chan_mode == TCH_AHS_MODE))
712 {
713 if (((next_time->fn_mod13_mod4 == 3) &&
714 ((chan_mode == TCH_AFS_MODE) || ((subchannel == 0)))) ||
715 ((next_time->fn_mod13_mod4 == 0) &&
716 ((chan_mode == TCH_AHS_MODE) && (subchannel == 1)))
717 )
718 {
719 if (dtx_dsp_interrupt)
720 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=1;
721 else
722 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=0;
723
724 }
725 }
726 // Fast DTX not supported
727 else
728 {
729 // No interrupt genaration
730 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=0;
731 }
732 #endif
733 }
734 #else
735 /*-------------------------------------------------------*/
736 /* l1ddsp_load_tch_param() */
737 /*-------------------------------------------------------*/
738 /* Parameters : */
739 /* Return : */
740 /* Functionality : */
741 /*-------------------------------------------------------*/
742 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
743 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
744 UWORD8 chan_type, UWORD8 subchannel,
745 UWORD8 tch_loop, UWORD8 sync_tch,
746 #if !FF_L1_IT_DSP_DTX
747 UWORD8 reset_sacch, UWORD8 vocoder_on)
748 #else
749 UWORD8 reset_sacch, UWORD8 vocoder_on,
750 BOOL dtx_dsp_interrupt)
751 #endif
752 #else
753 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
754 UWORD8 chan_type, UWORD8 subchannel,
755 #if !FF_L1_IT_DSP_DTX
756 UWORD8 tch_loop, UWORD8 sync_tch)
757 #else
758 UWORD8 tch_loop, UWORD8 sync_tch,
759 BOOL dtx_dsp_interrupt)
760 #endif
761 #endif
762 {
763 UWORD32 count_0;
764 UWORD32 count_1;
765 UWORD32 d_ctrl_tch;
766 UWORD32 d_fn;
767
768 // d_ctrl_tch
769 // ----------
770 // bit [0..3] -> b_chan_mode
771 // bit [4..7] -> b_chan_type
772 // bit [8] -> b_sync_tch_ul
773 // bit [9] -> b_sync_tch_dl
774 // bit [10] -> b_stop_tch_ul
775 // bit [11] -> b_stop_tch_dl
776 // bit [12..14] -> b_tch_loop
777 // bit [15] -> b_subchannel
778 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
779 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
780 (sync_tch<<B_SYNC_TCH_UL) | (sync_tch<<B_SYNC_TCH_DL) |
781 (tch_loop<<B_TCH_LOOP) | (reset_sacch<<B_RESET_SACCH) | (vocoder_on<<B_VOCODER_ON);
782 #else
783 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
784 (sync_tch<<B_SYNC_TCH_UL) | (sync_tch<<B_SYNC_TCH_DL) |
785 (tch_loop<<B_TCH_LOOP);
786 #endif
787
788 // d_fn
789 // ----
790 // bit [0..7] -> b_fn_report
791 // bit [8..15] -> b_fn_sid
792 d_fn = (next_time->fn_in_report) | ((next_time->fn%104)<<8);
793
794 // a_a5fn
795 // ------
796 // count_0 (a_a5fn[0]), bit [0..4] -> T2.
797 // count_0 (a_a5fn[1]), bit [5..10] -> T3.
798 // count_1 (a_a5fn[0]), bit [0..10] -> T1.
799 count_0 = ((UWORD16)next_time->t3 << 5) | (next_time->t2);
800 count_1 = (next_time->t1);
801
802 l1s_dsp_com.dsp_db_w_ptr->d_fn = d_fn; // write both Fn_sid, Fn_report.
803 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[0] = count_0; // cyphering FN part 1.
804 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[1] = count_1; // cyphering FN part 2.
805 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = d_ctrl_tch; // Channel config.
806 }
807 #endif
808
809 #if (L1_VOCODER_IF_CHANGE == 0)
810 // TODO: to be moved in API file (see BUG3093)
811 BOOL enable_tch_vocoder(BOOL vocoder)
812 {
813 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
814 // To enable the vocoder, we set the trigger => then handled in l1s_dedicated_mode_manager
815 #if (W_A_DSP_PR20037 == 1)
816 if ((vocoder==TRUE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_DISABLED))
817 {
818 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
819
820 #if ( L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
821 NU_Sleep(DSP_VOCODER_ON_TRANSITION); // DSP transition
822 #endif
823 }
824 // When vocoder_on = FALSE, vocoder module is not executed
825 else if ((vocoder==FALSE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_ENABLED))
826 {
827 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_DISABLE_REQ;
828 }
829 #else // W_A_DSP_PR20037 == 0
830 if (vocoder)
831 {
832 l1a_l1s_com.dedic_set.start_vocoder = TRUE;
833 }
834 // When vocoder_on = FALSE, vocoder module is not executed
835 else
836 {
837 l1a_l1s_com.dedic_set.vocoder_on = FALSE;
838 }
839 #endif // W_A_DSP_PR20037
840
841 return TRUE;
842 #else
843 return FALSE;
844 #endif
845 }
846 #endif // L1_VOCODER_IF_CHANGE
847 BOOL l1_select_mcsi_port(UWORD8 port)
848 {
849 #if ( (CHIPSET == 12) && (RF_FAM != 61) )
850 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = (API)port;
851 return TRUE;
852 #else
853 return FALSE;
854 #endif
855 }
856
857 // TODO: to be moved in API file
858
859 /*-------------------------------------------------------*/
860 /* l1ddsp_load_ciph_param() */
861 /*-------------------------------------------------------*/
862 /* Parameters : */
863 /* Return : */
864 /* Functionality : */
865 /*-------------------------------------------------------*/
866 void l1ddsp_load_ciph_param(UWORD8 a5mode,
867 T_ENCRYPTION_KEY *ciph_key)
868 {
869 // Store ciphering mode (0 for no ciphering) in MCU-DSP com.
870 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = a5mode; // A5 algorithm (0 for none).
871 // Store ciphering key.
872
873 #if (L1_A5_3 == 1)
874
875 if(a5mode == 3)
876 {
877 #if(OP_L1_STANDALONE != 1)
878 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
879 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
880 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
881 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
882 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[4] = (ciph_key->A[8]) | (ciph_key->A[9] << 8);
883 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[5] = (ciph_key->A[10]) | (ciph_key->A[11] << 8);
884 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[6] = (ciph_key->A[12]) | (ciph_key->A[13] << 8);
885 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[7] = (ciph_key->A[14]) | (ciph_key->A[15] << 8);
886 #else // (OP_L1_STANDALONE == 1)
887 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
888 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
889 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
890 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
891 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[4] = (ciph_key->A[8]) | (ciph_key->A[1] << 8);
892 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[5] = (ciph_key->A[10]) | (ciph_key->A[3] << 8);
893 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[6] = (ciph_key->A[12]) | (ciph_key->A[5] << 8);
894 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[7] = (ciph_key->A[14]) | (ciph_key->A[7] << 8);
895 #endif
896 }
897 else // a5mode == 1 or 2
898 {
899 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
900 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
901 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
902 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
903 }
904
905 #else
906
907 l1s_dsp_com.dsp_ndb_ptr->a_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
908 l1s_dsp_com.dsp_ndb_ptr->a_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
909 l1s_dsp_com.dsp_ndb_ptr->a_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
910 l1s_dsp_com.dsp_ndb_ptr->a_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
911
912 #endif
913 }
914
915 /*-------------------------------------------------------*/
916 /* l1ddsp_stop_tch() */
917 /*-------------------------------------------------------*/
918 /* Parameters : */
919 /* Return : */
920 /* Functionality : */
921 /*-------------------------------------------------------*/
922 void l1ddsp_stop_tch(void)
923 {
924 // Tch channel description.
925 // bit [10] -> b_stop_tch_ul, stop TCH/UL.
926 // bit [11] -> b_stop_tch_dl, stop TCH/DL.
927
928 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch |= 3 << B_STOP_TCH_UL;
929 }
930
931 /*-------------------------------------------------------*/
932 /* l1ddsp_meas_read() */
933 /*-------------------------------------------------------*/
934 /* Parameters : */
935 /* Return : */
936 /* Functionality : */
937 /*-------------------------------------------------------*/
938 void l1ddsp_meas_read(UWORD8 nbmeas, UWORD8 *pm)
939 {
940 UWORD8 i;
941
942 for (i= 0; i < nbmeas; i++)
943 {
944 pm[i] = ((l1s_dsp_com.dsp_db_r_ptr->a_pm[i] & 0xffff) >> 5);
945 }
946
947 #if TESTMODE
948 if(l1_config.TestMode)
949 l1tm.tmode_stats.pm_recent = l1s_dsp_com.dsp_db_r_ptr->a_pm[0] & 0xffff;
950 #endif
951 }
952
953 #if (AMR == 1)
954 /*-------------------------------------------------------*/
955 /* l1ddsp_load_amr_param() */
956 /*-------------------------------------------------------*/
957 /* Parameters : AMR configuration */
958 /* Return : none */
959 /* Functionality : Download the AMR configuration to the */
960 /* DSP via API */
961 /*-------------------------------------------------------*/
962 void l1ddsp_load_amr_param(T_AMR_CONFIGURATION amr_param, UWORD8 cmip)
963 {
964 // Clear the AMR API buffer
965 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = (API)0;
966 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = (API)0;
967 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = (API)0;
968 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = (API)0;
969
970 // Set the AMR parameters
971 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[NSCB_INDEX] |= (API)((amr_param.noise_suppression_bit & NSCB_MASK ) << NSCB_SHIFT);
972 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMUL_INDEX] |= (API)((amr_param.initial_codec_mode & ICM_MASK ) << ICMUL_SHIFT);
973 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMDL_INDEX] |= (API)((amr_param.initial_codec_mode & ICM_MASK ) << ICMDL_SHIFT);
974 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMIUL_INDEX] |= (API)((amr_param.initial_codec_mode_indicator & ICMI_MASK ) << ICMIUL_SHIFT);
975 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMIDL_INDEX] |= (API)((amr_param.initial_codec_mode_indicator & ICMI_MASK ) << ICMIDL_SHIFT);
976 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ACSUL_INDEX] |= (API)((amr_param.active_codec_set & ACS_MASK ) << ACSUL_SHIFT);
977 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ACSDL_INDEX] |= (API)((amr_param.active_codec_set & ACS_MASK ) << ACSDL_SHIFT);
978 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR1_INDEX] |= (API)((amr_param.threshold[0] & THR_MASK ) << THR1_SHIFT);
979 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR2_INDEX] |= (API)((amr_param.threshold[1] & THR_MASK ) << THR2_SHIFT);
980 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR3_INDEX] |= (API)((amr_param.threshold[2] & THR_MASK ) << THR3_SHIFT);
981 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST1_INDEX] |= (API)((amr_param.hysteresis[0] & HYST_MASK ) << HYST1_SHIFT);
982 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST2_INDEX] |= (API)((amr_param.hysteresis[1] & HYST_MASK ) << HYST2_SHIFT);
983 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST3_INDEX] |= (API)((amr_param.hysteresis[2] & HYST_MASK ) << HYST3_SHIFT);
984 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[CMIP_INDEX] |= (API)((cmip & CMIP_MASK ) << CMIP_SHIFT);
985 }
986 #endif
987
988 #if (L1_SAIC != 0)
989 /*-------------------------------------------------------*/
990 /* l1ddsp_load_swh_flag() */
991 /*-------------------------------------------------------*/
992 /* Parameters : SWH (Spatial Whitening) Flag */
993 /* Return : none */
994 /* Functionality : To write the d_swh_ApplyWhitening flag*/
995 /*-------------------------------------------------------*/
996 void l1ddsp_load_swh_flag (UWORD16 SWH_flag, UWORD16 SAIC_flag)
997 {
998
999 if(SAIC_flag)
1000 {
1001 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db = SAIC_ENABLE_DB;
1002 if(SWH_flag)
1003 {
1004 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db |= (0x01<< B_SWH_DB);
1005 }
1006 }
1007 else
1008 {
1009 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db = 0;
1010 }
1011 }
1012 #endif
1013
1014 /*-------------------------------------------------------*/
1015 /* l1ddsp_end_scenario() */
1016 /*-------------------------------------------------------*/
1017 /* Parameters : */
1018 /* Return : */
1019 /* Functionality : */
1020 /*-------------------------------------------------------*/
1021 void l1ddsp_end_scenario(UWORD8 type)
1022 {
1023 #if (CODE_VERSION == SIMULATION)
1024 #if (AUDIO_SIMULATION)
1025 switch(type)
1026 {
1027 case GSM_CTL:
1028 case GSM_MISC_CTL:
1029 // a DSP control for a GSM task or
1030 // a DSP control for a GSM and a MISC tasks
1031 //-----------------------------
1032 {
1033 // set DSP_ENB and DSP_PAG for communication interrupt
1034 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page;
1035 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1036
1037 // change DSP page pointer for next controle
1038 l1s_dsp_com.dsp_w_page ^= 1;
1039 }
1040 break;
1041
1042 case MISC_CTL:
1043 // a DSP control for a MISC task
1044 //------------------------------
1045 {
1046 // set only MISC task and reset MISC page
1047 // (don't change GSM PAGE).
1048 // set DSP communication Interrupt.
1049 // set DSP_ENB and the same DSP_PAG for communication interrupt
1050 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page^1;
1051 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1052 }
1053 break;
1054 }
1055 #else // NO AUDIO_SIMULATION
1056 // set DSP_ENB and DSP_PAG for communication interrupt
1057 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page;
1058 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1059
1060 // change DSP page pointer for next control
1061 l1s_dsp_com.dsp_w_page ^= 1;
1062 #endif // AUDIO_SIMULATION
1063
1064 #else // NOT_SIMULATION
1065 UWORD32 dsp_task;
1066 switch(type)
1067 {
1068 case GSM_CTL:
1069 // a DSP control for a GSM task
1070 //-----------------------------
1071 {
1072 // set only GSM task and GSM page
1073 dsp_task = B_GSM_TASK | l1s_dsp_com.dsp_w_page;
1074 // change DSP page pointer for next controle
1075 l1s_dsp_com.dsp_w_page ^= 1;
1076 }
1077 break;
1078
1079 case MISC_CTL:
1080 // a DSP control for a MISC task
1081 //------------------------------
1082 {
1083 UWORD32 previous_page = l1s_dsp_com.dsp_w_page ^ 1;
1084
1085 // set only MISC task and reset MISC page
1086 // (don't change GSM PAGE).
1087 // set DSP communication Interrupt.
1088 dsp_task = B_MISC_TASK | previous_page;
1089
1090 // Rem: DSP makes the DB header feedback even in case
1091 // of MISC task (like TONES). This created some
1092 // side effect which are "work-around" passing
1093 // the correct DB page to the DSP.
1094 }
1095 break;
1096
1097 case GSM_MISC_CTL:
1098 // a DSP control for a GSM and a MISC tasks
1099 //-----------------------------------------
1100 {
1101 // set GSM task, MISC task and GSM page bit.....
1102 dsp_task = B_GSM_TASK | B_MISC_TASK | l1s_dsp_com.dsp_w_page;
1103 // change DSP page pointer for next controle
1104 l1s_dsp_com.dsp_w_page ^= 1;
1105 }
1106 break;
1107
1108 #if 0 /* enable this after TCS211 reconstruction */
1109 default:
1110 dsp_task = 0;
1111 #endif
1112 }
1113
1114 // write dsp tasks.....
1115 #if (DSP >= 33)
1116 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = (API) dsp_task;
1117 #else
1118 l1s_dsp_com.dsp_param_ptr->d_dsp_page = (API) dsp_task;
1119 #endif
1120
1121 // Enable frame IT on next TDMA
1122 l1dmacro_set_frame_it();
1123
1124 #if (DSP >= 38)
1125 // DSP CPU load measurement - write logic (provide TDMA frame number to DSP)
1126 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_TDMA_FN))) = (API)l1s.actual_time.fn_mod42432;
1127 #endif
1128
1129 #endif // NOT_SIMULATION
1130 }
1131
1132 /*-------------------------------------------------------*/
1133 /* l1dtpu_meas() */
1134 /*-------------------------------------------------------*/
1135 /* Parameters : */
1136 /* Return : */
1137 /* Functionality : */
1138
1139 /* Locosto : should take additional Param of task */
1140
1141 /*-------------------------------------------------------*/
1142 void l1dtpu_meas(UWORD16 radio_freq,
1143 WORD8 agc,
1144 UWORD8 lna_off,
1145 UWORD16 win_id,
1146 UWORD16 tpu_synchro, UWORD8 adc_active
1147 #if(RF_FAM == 61)
1148 ,UWORD8 afc_mode
1149 ,UWORD8 if_ctl
1150 #endif
1151 )
1152
1153 {
1154
1155 WORD16 offset;
1156 WORD16 when;
1157 UWORD16 offset_chg;
1158
1159 #if TESTMODE
1160 if (!l1_config.agc_enable)
1161 {
1162 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1163 // corresponds to the lna_off bit
1164 agc = l1_config.tmode.rx_params.agc;
1165 lna_off = l1_config.tmode.rx_params.lna_off;
1166 }
1167 #endif // TESTMODE
1168
1169 // Compute offset
1170 offset_chg = ((win_id * BP_DURATION) >> BP_SPLIT_PW2);
1171 offset = tpu_synchro + offset_chg;
1172 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE;
1173
1174 // Compute offset change timing
1175 when = offset_chg + PROVISION_TIME - (l1_config.params.rx_synth_setup_time + EPSILON_OFFS);
1176 if(when < 0) when += TPU_CLOCK_RANGE;
1177
1178 // Program TPU scenario
1179 l1dmacro_offset (offset, when); // change TPU offset according to win_id
1180 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1181 if(adc_active == ACTIVE)
1182 l1dmacro_adc_read_rx(); // pgme ADC measurement
1183
1184 l1dmacro_agc (radio_freq, agc,lna_off
1185 #if (RF_FAM == 61)
1186 ,if_ctl
1187 #endif
1188 ); // pgme AGC.
1189 #if (CODE_VERSION == SIMULATION)
1190 l1dmacro_rx_ms (radio_freq, 0); // pgm PWR acquisition.
1191 #else
1192 #if (L1_MADC_ON == 1)
1193 #if (RF_FAM == 61)
1194 l1dmacro_rx_ms (radio_freq,adc_active); // pgm PWR acquisition.
1195 #endif
1196 #else
1197 l1dmacro_rx_ms (radio_freq); // pgm PWR acquisition.
1198 #endif
1199 #endif
1200 l1dmacro_offset (tpu_synchro, IMM); // restore offset
1201
1202 //Locosto
1203 #if(RF_FAM == 61)
1204 // L1_AFC_SCRIPT_MODE - This is specific to Locosto to make AFC script run after
1205 // the second power measurement during FBNEW
1206 if ((win_id == 0) || (afc_mode == L1_AFC_SCRIPT_MODE))
1207 #else
1208 if (win_id == 0)
1209 #endif
1210 {
1211 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1212 // NOTE: In Locosto AFC is in DRP not in triton
1213 l1ddsp_load_afc(l1s.afc);
1214 #endif
1215
1216 //Locosto
1217 #if(RF_FAM == 61)
1218 if(afc_mode != L1_AFC_NONE)
1219 {
1220 if(afc_mode == L1_AFC_SCRIPT_MODE)
1221 {
1222 l1dtpu_load_afc(l1s.afc); //Load the Initial afc value to the TPU. TPU would copy it to the DRP Wrapper Mem.
1223 }
1224 else
1225 {
1226 l1ddsp_load_afc(l1s.afc);
1227 }
1228 }
1229 #endif
1230 // end Locosto
1231 }
1232 }
1233
1234 /*-------------------------------------------------------*/
1235 /* l1dtpu_neig_fb() */
1236 /*-------------------------------------------------------*/
1237 /* Parameters : */
1238 /* Return : */
1239 /* Functionality : */
1240 /*-------------------------------------------------------*/
1241 void l1dtpu_neig_fb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off)
1242 {
1243 #if TESTMODE
1244 if (!l1_config.agc_enable)
1245 {
1246 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1247 // corresponds to the lna_off bit
1248 agc = l1_config.tmode.rx_params.agc;
1249 lna_off = l1_config.tmode.rx_params.lna_off;
1250 }
1251 #endif
1252
1253 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1254 l1dmacro_agc (radio_freq,agc, lna_off
1255 #if (RF_FAM == 61)
1256 ,IF_120KHZ_DSP
1257 #endif
1258 ); // pgme AGC.
1259 #if (L1_MADC_ON == 1)
1260 #if (RF_FAM == 61)
1261 l1dmacro_rx_fb (radio_freq,INACTIVE); // pgm FB acquisition.
1262 #endif
1263 #else
1264 l1dmacro_rx_fb (radio_freq); // pgm FB acquisition.
1265 #endif
1266 }
1267
1268 /*-------------------------------------------------------*/
1269 /* l1dtpu_neig_fb26() */
1270 /*-------------------------------------------------------*/
1271 /* Parameters : */
1272 /* Return : */
1273 /* Functionality : */
1274 /*-------------------------------------------------------*/
1275 void l1dtpu_neig_fb26(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 offset_serv)
1276 {
1277 WORD16 offset;
1278
1279 #if TESTMODE
1280 if (!l1_config.agc_enable)
1281 {
1282 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1283 // corresponds to the lna_off bit
1284 agc = l1_config.tmode.rx_params.agc;
1285 lna_off = l1_config.tmode.rx_params.lna_off;
1286 }
1287 #endif
1288
1289 // Compute offset
1290 offset = offset_serv + l1_config.params.fb26_anchoring_time;
1291 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE;
1292
1293 // Program TPU scenario
1294 l1dmacro_offset (offset, l1_config.params.fb26_change_offset_time);
1295 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1296 l1dmacro_agc (radio_freq,agc, lna_off
1297 #if (RF_FAM == 61)
1298 ,IF_120KHZ_DSP
1299 #endif
1300 ); // pgme AGC.
1301 #if (L1_MADC_ON == 1)
1302 #if (RF_FAM == 61)
1303 l1dmacro_rx_fb26 (radio_freq, INACTIVE); // pgm FB acquisition.
1304 #endif
1305 #else
1306 l1dmacro_rx_fb26 (radio_freq); // pgm FB acquisition.
1307 #endif
1308 l1dmacro_offset (offset_serv, IMM); // restore offset
1309 }
1310
1311 /*-------------------------------------------------------*/
1312 /* l1dtpu_neig_sb() */
1313 /*-------------------------------------------------------*/
1314 /* Parameters : */
1315 /* Return : */
1316 /* Functionality : */
1317 /*-------------------------------------------------------*/
1318 void l1dtpu_neig_sb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1319 UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag,
1320 UWORD8 attempt
1321 #if (RF_FAM == 61)
1322 ,UWORD8 if_ctl
1323 #endif
1324 )
1325 {
1326 UWORD16 offset_neigh;
1327
1328 #if TESTMODE
1329 if (!l1_config.agc_enable)
1330 {
1331 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1332 // corresponds to the lna_off bit
1333 agc = l1_config.tmode.rx_params.agc;
1334 lna_off = l1_config.tmode.rx_params.lna_off;
1335 }
1336 #endif
1337
1338 // compute offset neighbour...
1339 offset_neigh = offset_serv + time_alignmt;
1340 if(offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1341
1342 // load OFFSET with NEIGHBOUR value.
1343 l1dmacro_offset (offset_neigh, l1_config.params.rx_change_offset_time);
1344
1345 // Insert 1 NOP to correct the EPSILON_SYNC side effect.
1346 if(attempt != 2)
1347 if(time_alignmt >= (TPU_CLOCK_RANGE - EPSILON_SYNC))
1348 l1dmacro_offset (offset_neigh, 0); // load OFFSET with NEIGHBOUR value.
1349
1350 l1dmacro_rx_synth(radio_freq); // pgme SYNTH.
1351 l1dmacro_agc (radio_freq, agc, lna_off
1352 #if (RF_FAM == 61)
1353 ,if_ctl
1354 #endif
1355 ); // pgme AGC.
1356 #if (L1_MADC_ON == 1)
1357 #if (RF_FAM == 61)
1358 l1dmacro_rx_sb (radio_freq,INACTIVE); // pgm SB acquisition.
1359 #endif
1360 #else
1361 l1dmacro_rx_sb (radio_freq); // pgm SB acquisition.
1362 #endif
1363
1364 // Restore offset with serving value.
1365 if(reload_flag == TRUE)
1366 {
1367 l1dmacro_offset (offset_serv, IMM);
1368 }
1369 }
1370 /*-------------------------------------------------------*/
1371 /* l1dtpu_neig_fbsb() */
1372 /*-------------------------------------------------------*/
1373 /* Parameters : */
1374 /* Return : */
1375 /* Functionality : */
1376 /*-------------------------------------------------------*/
1377 #if ((REL99 == 1) && (FF_BHO == 1))
1378 /*void l1dtpu_neig_fbsb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off
1379 #if (RF_FAM == 61)
1380 ,UWORD8 if_ctl
1381 #endif
1382 )*/
1383 void l1dtpu_neig_fbsb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off)
1384 {
1385 #if TESTMODE
1386 if (!l1_config.agc_enable)
1387 {
1388 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1389 // corresponds to the lna_off bit
1390 agc = l1_config.tmode.rx_params.agc;
1391 lna_off = l1_config.tmode.rx_params.lna_off;
1392 }
1393 #endif // TESTMODE
1394
1395 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1396 /*l1dmacro_agc(radio_freq, agc, lna_off
1397 #if (RF_FAM == 61)
1398 ,if_ctl
1399 #endif
1400 ); // pgme AGC.
1401 */
1402 l1dmacro_agc (radio_freq,agc, lna_off
1403 #if (RF_FAM == 61)
1404 ,L1_CTL_LOW_IF
1405 #endif
1406 ); // pgme AGC.
1407 #if (L1_MADC_ON == 1)
1408 #if (RF_FAM == 61)
1409 l1dmacro_rx_fbsb(radio_freq,INACTIVE); // pgm FB acquisition.
1410 #endif
1411 #else
1412 l1dmacro_rx_fbsb(radio_freq); // pgm FB acquisition.- sajal commented
1413 #endif
1414 }
1415 #endif // #if ((REL99 == 1) && (FF_BHO == 1))
1416 /*-------------------------------------------------------*/
1417 /* l1dtpu_neig_sb26() */
1418 /*-------------------------------------------------------*/
1419 /* Parameters : */
1420 /* Return : */
1421 /* Functionality : */
1422 /*-------------------------------------------------------*/
1423 void l1dtpu_neig_sb26(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 time_alignmt,
1424 UWORD32 fn_offset, UWORD32 offset_serv
1425 #if (RF_FAM == 61)
1426 ,UWORD8 if_ctl
1427 #endif
1428 )
1429 {
1430 UWORD16 offset_neigh;
1431
1432 #if TESTMODE
1433 if (!l1_config.agc_enable)
1434 {
1435 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1436 // corresponds to the lna_off bit
1437 agc = l1_config.tmode.rx_params.agc;
1438 lna_off = l1_config.tmode.rx_params.lna_off;
1439 }
1440 #endif
1441
1442 // compute offset neighbour...
1443 offset_neigh = offset_serv + time_alignmt;
1444 if(offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1445
1446 if(fn_offset != 0)
1447 l1dmacro_offset (offset_neigh, 0); // 1 NOP in some case
1448 else
1449 l1dmacro_offset (offset_neigh, l1_config.params.fb26_change_offset_time);
1450
1451 l1dmacro_rx_synth(radio_freq); // pgme SYNTH.
1452 l1dmacro_agc(radio_freq, agc, lna_off
1453 #if (RF_FAM == 61)
1454 ,if_ctl
1455 #endif
1456 ); // pgme AGC.
1457 #if (L1_MADC_ON == 1)
1458 #if (RF_FAM == 61)
1459 l1dmacro_rx_sb (radio_freq, INACTIVE); // pgm SB acquisition.
1460 #endif
1461 #else
1462 l1dmacro_rx_sb (radio_freq); // pgm SB acquisition.
1463 #endif
1464 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1465 }
1466
1467 /*-------------------------------------------------------*/
1468 /* l1dtpu_serv_rx_nb() */
1469 /*-------------------------------------------------------*/
1470 /* Parameters : */
1471 /* Return : */
1472 /* Functionality : */
1473 /*-------------------------------------------------------*/
1474 void l1dtpu_serv_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1475 UWORD32 synchro_serv,UWORD32 new_offset,BOOL change_offset,
1476 UWORD8 adc_active
1477 #if(RF_FAM == 61)
1478 , UWORD8 csf_filter_choice
1479 , UWORD8 if_ctl
1480 #endif
1481 #if (NEW_SNR_THRESHOLD == 1)
1482 , UWORD8 saic_flag
1483 #endif/* NEW_SNR_THRESHOLD == 1*/
1484 )
1485 {
1486
1487 #if (CODE_VERSION == SIMULATION)
1488 UWORD32 tpu_w_page;
1489
1490 if (hw.tpu_r_page==0)
1491 tpu_w_page=1;
1492 else
1493 tpu_w_page=0;
1494
1495 // Give the Ts related to the L1s
1496 hw.rx_id[tpu_w_page][0]= ((TPU_CLOCK_RANGE+new_offset-synchro_serv)%TPU_CLOCK_RANGE)/TN_WIDTH;
1497 hw.num_rx[tpu_w_page][0]=1;
1498 hw.rx_group_id[tpu_w_page]=1;
1499 #endif
1500
1501 #if TESTMODE
1502 if (!l1_config.agc_enable)
1503 {
1504 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1505 // corresponds to the lna_off bit
1506 agc = l1_config.tmode.rx_params.agc;
1507 lna_off = l1_config.tmode.rx_params.lna_off;
1508 }
1509 #endif
1510
1511 l1dmacro_synchro (l1_config.params.rx_change_synchro_time, synchro_serv); // Adjust serving OFFSET.
1512
1513 #if L2_L3_SIMUL
1514 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1515 buffer_trace(3, 0x43, synchro_serv,l1s.actual_time.fn,0);
1516 #endif
1517 #endif
1518
1519 // Need to slide offset to cope with the new synchro.
1520 if(change_offset)
1521 l1dmacro_offset(new_offset, l1_config.params.rx_change_offset_time);
1522
1523 l1dmacro_rx_synth(radio_freq); // load SYNTH.
1524 if(adc_active == ACTIVE)
1525 l1dmacro_adc_read_rx(); // pgme ADC measurement
1526
1527 l1dmacro_agc (radio_freq, agc, lna_off
1528 #if (RF_FAM == 61)
1529 ,if_ctl
1530 #endif
1531 );
1532
1533 #if TESTMODE && (CODE_VERSION != SIMULATION)
1534 // Continuous mode: Rx continuous scenario only on START_RX state.
1535 if ((l1_config.TestMode) &&
1536 (l1_config.tmode.rf_params.tmode_continuous == TM_START_RX_CONTINUOUS))
1537 #if (L1_MADC_ON == 1)
1538 #if (RF_FAM == 61)
1539 l1dmacro_rx_cont (FALSE, radio_freq,adc_active,csf_filter_choice
1540 #if (NEW_SNR_THRESHOLD == 1)
1541 ,saic_flag
1542 #endif /* NEW_SNR_THRESHOLD*/
1543 );
1544 #endif /* RF_FAM == 61*/
1545 #else /* L1_MADC_ON == 1 */
1546 #if (RF_FAM == 61)
1547 l1dmacro_rx_cont (FALSE, radio_freq,csf_filter_choice);
1548 #else
1549 l1dmacro_rx_cont (FALSE, radio_freq);
1550 #endif
1551 #endif
1552 //TBD Danny New MAcro for Cont Tx reqd, to use only External Trigger
1553 else
1554 #endif
1555 #if ( L1_MADC_ON == 1)
1556 #if (RF_FAM == 61)
1557 l1dmacro_rx_nb (radio_freq, adc_active, csf_filter_choice
1558 #if (NEW_SNR_THRESHOLD == 1)
1559 ,saic_flag
1560 #endif /* NEW_SNR_THRESHOLD*/
1561 ); // RX window for NB.
1562 #endif /* RF_FAM == 61*/
1563 #else /* L1_MADC_ON == 1*/
1564 #if (RF_FAM == 61)
1565 l1dmacro_rx_nb (radio_freq, csf_filter_choice); // RX window for NB.
1566 #else
1567 l1dmacro_rx_nb (radio_freq); // RX window for NB.
1568 #endif
1569 #endif
1570
1571 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1572 l1ddsp_load_afc(l1s.afc);
1573 #endif
1574 #if (RF_FAM == 61)
1575 l1dtpu_load_afc(l1s.afc);
1576 #endif
1577
1578
1579 if(change_offset)
1580 l1dmacro_offset(synchro_serv, IMM); // Restore offset.
1581 }
1582
1583 /*-------------------------------------------------------*/
1584 /* l1dtpu_serv_tx_nb() */
1585 /*-------------------------------------------------------*/
1586 /* Parameters : */
1587 /* Return : */
1588 /* Functionality : */
1589 /*-------------------------------------------------------*/
1590 void l1dtpu_serv_tx_nb(UWORD16 radio_freq, UWORD8 timing_advance,
1591 UWORD32 offset_serv, UWORD8 txpwr, UWORD8 adc_active)
1592 {
1593 WORD32 time;
1594 UWORD32 offset_tx;
1595 UWORD32 timing_advance_in_qbit = (UWORD32)timing_advance << 2;
1596
1597 #if (CODE_VERSION == SIMULATION)
1598 UWORD32 tpu_w_page;
1599
1600 if (hw.tpu_r_page==0)
1601 tpu_w_page=1;
1602 else
1603 tpu_w_page=0;
1604
1605 hw.tx_id[tpu_w_page][0]=3;// MS synchronized on TN=0 for RX => TN=3 for TX
1606 hw.num_tx[tpu_w_page][0]=1;
1607 hw.tx_group_id[tpu_w_page]=1;
1608 #endif
1609
1610 // Reset timing advance if TA_ALGO not enabled.
1611 #if !TA_ALGO
1612 timing_advance_in_qbit = 0;
1613 #endif
1614
1615 // Compute offset value for TX.
1616 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX !
1617 offset_tx = (offset_serv + TIME_OFFSET_TX-l1_config.params.prg_tx_gsm - timing_advance_in_qbit) ;
1618 if (offset_tx >= TPU_CLOCK_RANGE) offset_tx -= TPU_CLOCK_RANGE;
1619
1620 // Check that RX controle has been already installed.
1621 // Offset for TX must be set an immediately if RX is there else
1622 // it must be performed EPSILON_SYNC before current offset time.
1623 if( l1s.tpu_ctrl_reg & CTRL_RX )
1624 time = l1_config.params.tx_change_offset_time - l1_config.params.prg_tx_gsm;
1625 else
1626 time = TPU_CLOCK_RANGE - EPSILON_SYNC;
1627
1628 l1dmacro_offset (offset_tx, time); // load OFFSET for TX before each burst.
1629
1630 #if L2_L3_SIMUL
1631 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1632 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0);
1633 #endif
1634 #endif
1635
1636 l1dmacro_tx_synth(radio_freq); // load SYNTH.
1637 #if TESTMODE && (CODE_VERSION != SIMULATION)
1638 // Continuous mode: Tx continuous scenario only on START_TX state.
1639 #if (RF_FAM != 61)
1640 if ((l1_config.TestMode) &&
1641 (l1_config.tmode.rf_params.tmode_continuous == TM_START_TX_CONTINUOUS))
1642 l1dmacro_tx_cont (radio_freq, txpwr); // TX window for NB.
1643 else
1644 #endif // RF_FAM != 61
1645 #if (RF_FAM == 61)
1646 // NOTE: In Test Mode and in TX Continuous, APC control is in manual mode
1647 // This is done in l1tm_async.c
1648 if ((l1_config.TestMode) &&
1649 (l1_config.tmode.rf_params.tmode_continuous == TM_START_TX_CONTINUOUS))
1650 {
1651 // NOTE: APC is set in manual mode from l1tm_async.c
1652 l1dmacro_tx_cont (radio_freq, txpwr); // TX window for NB.
1653 }
1654 else
1655 #endif // RF_FAM == 61
1656 #endif
1657 l1dmacro_tx_nb (radio_freq, txpwr, adc_active); // TX window for NB.
1658 // TX window for NB.
1659 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1660
1661 #if L2_L3_SIMUL
1662 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1663 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0);
1664 #endif
1665 #endif
1666 }
1667
1668 /*-------------------------------------------------------*/
1669 /* l1dtpu_neig_rx_nb() */
1670 /*-------------------------------------------------------*/
1671 /* Parameters : */
1672 /* Return : */
1673 /* Functionality : */
1674 /*-------------------------------------------------------*/
1675 void l1dtpu_neig_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1676 UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag,
1677 UWORD8 nop
1678 #if (RF_FAM == 61)
1679 ,UWORD8 if_ctl
1680 #endif
1681 #if (NEW_SNR_THRESHOLD == 1)
1682 ,UWORD8 saic_flag
1683 #endif /* NEW_SNR_THRESHOLD*/
1684 )
1685 {
1686 UWORD32 offset_neigh;
1687 #if (RF_FAM == 61)
1688 // By default we choose the hardware filter for neighbour Normal Bursts
1689 UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER;
1690 #endif
1691
1692 #if TESTMODE
1693 if (!l1_config.agc_enable)
1694 {
1695 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1696 // corresponds to the lna_off bit
1697 agc = l1_config.tmode.rx_params.agc;
1698 lna_off = l1_config.tmode.rx_params.lna_off;
1699 }
1700 #endif
1701
1702 // compute offset neighbour...
1703 offset_neigh = (offset_serv + time_alignmt) ;
1704 if (offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1705
1706 l1dmacro_offset (offset_neigh, l1_config.params.rx_change_offset_time); // load OFFSET with NEIGHBOUR value.
1707 // Insert 1 NOP to correct the EPSILON_SYNC side effect
1708 if (nop ==1) l1dmacro_offset (offset_neigh,0);
1709
1710
1711 l1dmacro_rx_synth(radio_freq); // load SYNTH.
1712 l1dmacro_agc (radio_freq, agc, lna_off
1713 #if (RF_FAM == 61)
1714 ,if_ctl
1715 #endif
1716 );
1717 #if (L1_MADC_ON == 1)
1718 #if (RF_FAM == 61)
1719 l1dmacro_rx_nb (radio_freq, INACTIVE, csf_filter_choice
1720 #if (NEW_SNR_THRESHOLD == 1)
1721 ,saic_flag
1722 #endif /* NEW_SNR_THRESHOLD*/
1723 ) ; // RX window for NB.
1724 #endif /* RF_FAM == 61*/
1725 #else /* L1_MADC_ON == 1*/
1726 #if (RF_FAM == 61)
1727 l1dmacro_rx_nb (radio_freq, csf_filter_choice); // RX window for NB.
1728 #else
1729 l1dmacro_rx_nb (radio_freq); // RX window for NB.
1730 #endif
1731 #endif
1732
1733 // Restore offset with serving value.
1734 if(reload_flag == TRUE)
1735 l1dmacro_offset (offset_serv, IMM);
1736
1737 }
1738
1739 /*-------------------------------------------------------*/
1740 /* l1dtpu_serv_tx_ra() */
1741 /*-------------------------------------------------------*/
1742 /* Parameters : "burst_id" gives the burst identifier */
1743 /* which is used for offset management. */
1744 /* Return : */
1745 /* Functionality : */
1746 /*-------------------------------------------------------*/
1747 void l1dtpu_serv_tx_ra(UWORD16 radio_freq, UWORD32 offset_serv, UWORD8 txpwr, UWORD8 adc_active)
1748 {
1749 WORD32 time;
1750 UWORD32 offset_tx;
1751
1752 // Compute offset value for TX.
1753 // Rem: Timing Advance is always 0 for a RA.
1754 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX !
1755 offset_tx = (offset_serv + TIME_OFFSET_TX-l1_config.params.prg_tx_gsm);
1756 if (offset_tx >= TPU_CLOCK_RANGE) offset_tx -= TPU_CLOCK_RANGE;
1757
1758 // Check that RX controle has been already installed.
1759 // Offset for TX must be set an immediately if RX is there else
1760 // it must be performed EPSILON_SYNC before current offset time.
1761 if( l1s.tpu_ctrl_reg & CTRL_RX )
1762 time = l1_config.params.tx_change_offset_time - l1_config.params.prg_tx_gsm;
1763 else
1764 time = TPU_CLOCK_RANGE - EPSILON_SYNC;
1765
1766 l1dmacro_offset (offset_tx, time); // load OFFSET for TX before each burst.
1767 #if L2_L3_SIMUL
1768 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1769 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0);
1770 #endif
1771 #endif
1772 l1dmacro_tx_synth(radio_freq); // load SYNTH.
1773 l1dmacro_tx_ra (radio_freq, txpwr,adc_active); // TX window for RA.
1774 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1775 #if L2_L3_SIMUL
1776 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1777 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0);
1778 #endif
1779 #endif
1780 }
1781
1782 /*-------------------------------------------------------*/
1783 /* l1dtpu_end_scenario() */
1784 /*-------------------------------------------------------*/
1785 /* Parameters : */
1786 /* Return : */
1787 /* Functionality : */
1788 /*-------------------------------------------------------*/
1789 void l1dtpu_end_scenario(void)
1790 {
1791
1792 // write IDLE at end of TPU page
1793 // TPU_ENB and TPU_PAG are set in L1DMACRO_IDLE(). The TPU change
1794 // is executed by the TPU itself and the TPU pointer is reset to
1795 // start of page by l1dmacro_idle();
1796 l1dmacro_idle();
1797
1798 #if (CODE_VERSION == SIMULATION)
1799 #if LOGTPU_TRACE
1800 log_macro();
1801 #endif
1802 #endif
1803 // init pointer within new TPU page at 1st line
1804 #if (CODE_VERSION == SIMULATION)
1805 // set TPU_ENB, TPU_PAG for communication interrupt
1806 l1s_tpu_com.reg_cmd->tpu_pag_bit = l1s_tpu_com.tpu_w_page;
1807 l1s_tpu_com.reg_cmd->tpu_enb_bit = ON;
1808
1809 // change TPU and DSP page pointer for next control
1810 l1s_tpu_com.tpu_w_page ^= 1;
1811
1812 // points on new "write TPU page"...
1813 l1s_tpu_com.tpu_page_ptr=&(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
1814
1815 #endif
1816
1817 }
1818
1819 /*-------------------------------------------------------*/
1820 /* l1d_reset_hw() */
1821 /*-------------------------------------------------------*/
1822 /* Parameters : */
1823 /* Return : */
1824 /* Functionality : */
1825 /*-------------------------------------------------------*/
1826 void l1d_reset_hw(UWORD32 offset_value)
1827 {
1828 #if (CODE_VERSION == SIMULATION)
1829 // Reset DSP write/read page, Reset TPU write page, reset "used" flag.
1830 l1s_dsp_com.dsp_w_page = 0;
1831 l1s_dsp_com.dsp_r_page = 0;
1832 l1s_tpu_com.tpu_w_page = 0;
1833 l1s_dsp_com.dsp_r_page_used = 0;
1834
1835 // Reset communication pointers.
1836 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb); // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
1837 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[l1s_dsp_com.dsp_r_page]); // MCU<->DSP comm. read page (Double Buffered comm. memory).
1838 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[l1s_dsp_com.dsp_w_page]); // MCU<->DSP comm. write page (Double Buffered comm. memory).
1839
1840 // Reset task commands.
1841 l1s_dsp_com.dsp_db_w_ptr->d_task_d = NO_DSP_TASK; // Init. RX task to NO TASK.
1842 l1s_dsp_com.dsp_db_w_ptr->d_task_u = NO_DSP_TASK; // Init. TX task to NO TASK.
1843 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = NO_DSP_TASK; // Init. RA task to NO TASK.
1844 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NO_DSP_TASK; // Init. MONITORING task to NO TASK.
1845
1846
1847 //Reset the TCH channel description
1848 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = 0;
1849
1850 #if (L1_GPRS)
1851 // Reset communication pointers.
1852 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[l1s_dsp_com.dsp_r_page]);
1853 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[l1s_dsp_com.dsp_w_page]);
1854
1855 // Reset MCU->DSP page.
1856 l1ps_reset_db_mcu_to_dsp(l1ps_dsp_com.pdsp_db_w_ptr);
1857 #endif // L1_GPRS
1858
1859 // Direct access to TPU_RESET_BIT.
1860 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // Reset TPU.
1861
1862 // Reset TPU_ENB, DSP_ENB and TPU_PAG, DSP_PAG for communication interrupt
1863 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
1864 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0;
1865 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
1866 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF;
1867
1868 // Init pointer within TPU page 0 at 1st line
1869 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[0].line[0]);
1870
1871 // Load offset register according to serving cell.
1872 l1dmacro_offset(offset_value, IMM);
1873
1874 #else // NOT_SIMULATION
1875
1876 // Reset DSP write/read page, Reset TPU write page, reset "used" flag.
1877 l1s_dsp_com.dsp_w_page = 0;
1878 l1s_dsp_com.dsp_r_page = 0;
1879 l1s_tpu_com.tpu_w_page = 0;
1880 l1s_dsp_com.dsp_r_page_used = 0;
1881
1882 // Reset communication pointers.
1883 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
1884 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0; // MCU<->DSP comm. read page (Double Buffered comm. memory).
1885 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0; // MCU<->DSP comm. write page (Double Buffered comm. memory).
1886 l1s_dsp_com.dsp_param_ptr= (T_PARAM_MCU_DSP *) PARAM_ADR;
1887
1888 #if (DSP == 38) || (DSP == 39)
1889 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0;
1890 #endif
1891
1892 // Reset task commands.
1893 l1s_dsp_com.dsp_db_w_ptr->d_task_d = NO_DSP_TASK; // Init. RX task to NO TASK.
1894 l1s_dsp_com.dsp_db_w_ptr->d_task_u = NO_DSP_TASK; // Init. TX task to NO TASK.
1895 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = NO_DSP_TASK; // Init. RA task to NO TASK.
1896 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NO_DSP_TASK; // Init. MONITORING task to NO TASK.
1897
1898 //Reset the TCH channel description
1899 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = 0;
1900
1901 // Clear DSP_PAG bit
1902 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
1903 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = 0;
1904 #else
1905 l1s_dsp_com.dsp_param_ptr->d_dsp_page = 0;
1906 #endif
1907
1908 #if (L1_GPRS)
1909 // Reset communication pointers.
1910 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
1911 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS;
1912 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS;
1913 l1ps_dsp_com.pdsp_param_ptr= (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
1914
1915 // Reset MCU->DSP page.
1916 l1ps_reset_db_mcu_to_dsp(l1ps_dsp_com.pdsp_db_w_ptr);
1917 #endif // L1_GPRS
1918
1919 #if (DSP_DEBUG_TRACE_ENABLE == 1)
1920 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0;
1921 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1;
1922 #endif
1923
1924 // Reset TPU and Reload offset register with Serving value.
1925 // Clear TPU_PAG
1926 l1dmacro_reset_hw(offset_value);
1927 #endif // NOT_SIMULATION
1928 }
1929
1930
1931 #if(RF_FAM == 61)
1932
1933 /*-------------------------------------------------------*/
1934 /* l1apc_init_ramp_tables() */
1935 /*-------------------------------------------------------*/
1936 /* Parameters : void */
1937 /* Return : void */
1938 /* Functionality : This would copy the Ramp table */
1939 /* values to the MCU DSP API */
1940 /*-------------------------------------------------------*/
1941 void l1dapc_init_ramp_tables(void)
1942 {
1943
1944 #if (CODE_VERSION == SIMULATION)
1945 // Do Nothing there is no APC task
1946 #else
1947 #if ( DSP == 38) || (DSP == 39)
1948 // Load RAMP up/down in NDB memory...
1949 if (l1_config.tx_pwr_code == 0)
1950 {
1951 Cust_get_ramp_tab( l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp,
1952 0 /* not used */,
1953 0 /* not used */,
1954 1 /* arbitrary value for arfcn*/);
1955
1956 }
1957 else
1958 {
1959 Cust_get_ramp_tab( l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp,
1960 5 /* arbitrary value working in any case */,
1961 5 /* arbitrary value working in any case */,
1962 1 /* arbitrary value for arfcn*/);
1963 }
1964 #endif
1965 // Is it required to load ramptables for GPRS a_drp2_ramp_gprs
1966
1967 #endif
1968
1969 }
1970
1971
1972
1973 /*-------------------------------------------------------*/
1974 /* l1ddsp_apc_load_apcctrl2 */
1975 /*-------------------------------------------------------*/
1976 /* Parameters : void */
1977 /* Return : void */
1978 /* Functionality : This would copy the Ramp table */
1979 /* values to the MCU DSP API */
1980 /*-------------------------------------------------------*/
1981 void l1ddsp_apc_load_apcctrl2(UWORD16 apcctrl2)
1982 {
1983 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 = ((apcctrl2) | (0x8000));
1984 }
1985
1986 /*-------------------------------------------------------*/
1987 /* l1ddsp_apc_set_manual_mode */
1988 /*-------------------------------------------------------*/
1989 /* Parameters : void */
1990 /* Return : void */
1991 /* Functionality : This would set the APC in manual */
1992 /* OR external trigger mode */
1993 /*-------------------------------------------------------*/
1994 void l1ddsp_apc_set_manual_mode(void)
1995 {
1996 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 |= ((APC_APC_MODE) | (0x8000));
1997 }
1998
1999 /*-------------------------------------------------------*/
2000 /* l1ddsp_apc_set_automatic_mode */
2001 /*-------------------------------------------------------*/
2002 /* Parameters : void */
2003 /* Return : void */
2004 /* Functionality : This would set APC in automatic */
2005 /* OR internal sequencer mode */
2006 /*-------------------------------------------------------*/
2007 void l1ddsp_apc_set_automatic_mode(void)
2008 {
2009 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 &= ~(APC_APC_MODE);
2010 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 |= (0x8000);
2011 }
2012
2013 #ifdef TESTMODE
2014
2015 /*-------------------------------------------------------*/
2016 /* l1ddsp_apc_load_apclev */
2017 /*-------------------------------------------------------*/
2018 /* Parameters : void */
2019 /* Return : void */
2020 /* Functionality : This function writes the apclev */
2021 /* val into the APCLEV register via DSP */
2022 /* NOTE: Used only in TESTMODE and only when */
2023 /* l1_config.tmode.rf_params.down_up == TMODE_UPLINK; */
2024 /*-------------------------------------------------------*/
2025 void l1ddsp_apc_load_apclev(UWORD16 apclev)
2026 {
2027 l1s_dsp_com.dsp_ndb_ptr->d_apclev = ((apclev) | (0x8000));
2028 }
2029
2030
2031 #endif // TESTMODE
2032
2033 #endif
2034 #if FF_L1_IT_DSP_DTX
2035 /*-------------------------------------------------------*/
2036 /* l1ddsp_dtx_interrupt_pending() */
2037 /*-------------------------------------------------------*/
2038 /* Parameters : */
2039 /* Return : DTX interrupt status */
2040 /* Functionality : Test and clear the DTX IT pending */
2041 /* flag for DSP ISR screening purpose */
2042 /*-------------------------------------------------------*/
2043 BOOL l1ddsp_dtx_interrupt_pending(void)
2044 {
2045 if (l1s_dsp_com.dsp_ndb_ptr->d_dsp_hint_flag & (2 << B_DTX_HINT_ISSUED))
2046 {
2047 // Flag HISR to be scheduled
2048 l1a_apihisr_com.dtx.pending = TRUE;
2049 // Clear API ISR condition
2050 l1s_dsp_com.dsp_ndb_ptr->d_dsp_hint_flag &= ~(2 << B_DTX_HINT_ISSUED);
2051 return TRUE;
2052 }
2053 else
2054 return FALSE;
2055 }
2056 #endif
2057
2058
2059 #define L1_DEBUG_IQ_DUMP 0
2060
2061 #if (L1_DEBUG_IQ_DUMP == 1)
2062
2063 #define IQ_DUMP_MAX_LOG_SIZE (400) /* i.e. 200 I-Q Sample Pair */
2064 #define IQ_DUMP_BUFFER_SIZE (1280)
2065 #define L1_DSP_DUMP_IQ_BUFFER_PAGE0 (0xFFD00000 + ((0x2000 - 0x800)*2))
2066 #define L1_DSP_DUMP_IQ_BUFFER_PAGE1 (0xFFD00000 + ((0x2190 - 0x800)*2))
2067
2068 typedef struct
2069 {
2070 UWORD8 task;
2071 UWORD8 hole;
2072 UWORD16 size;
2073 UWORD16 fn_mod42432;
2074 UWORD16 iq_sample[IQ_DUMP_MAX_LOG_SIZE];
2075 }T_IQ_LOG_BUFFER;
2076
2077 #pragma DATA_SECTION(iq_dump_buffer,".debug_data");
2078 T_IQ_LOG_BUFFER iq_dump_buffer[IQ_DUMP_BUFFER_SIZE];
2079
2080 UWORD32 iq_dump_buffer_log_index = 0;
2081 UWORD32 iq_overflow_ind=0;
2082
2083 void l1ddsp_read_iq_dump(UWORD8 task)
2084 {
2085 UWORD16 *p_dsp_iq_buffer_ptr;
2086 UWORD16 size;
2087 int i;
2088
2089 /* get the page logic*/
2090 p_dsp_iq_buffer_ptr = (UWORD16 *)(L1_DSP_DUMP_IQ_BUFFER_PAGE0);
2091 if(l1s_dsp_com.dsp_r_page){
2092 p_dsp_iq_buffer_ptr = (UWORD16 *)(L1_DSP_DUMP_IQ_BUFFER_PAGE1);
2093 }
2094
2095 /* */
2096 size = *p_dsp_iq_buffer_ptr;
2097
2098 if(size == 0)
2099 return;
2100
2101 /* size given by DSP is in units of I-Q sample pair */
2102 if(size > (IQ_DUMP_MAX_LOG_SIZE /2)){
2103 size = (IQ_DUMP_MAX_LOG_SIZE/2);
2104 }
2105
2106 /* make size as zero again */
2107 *p_dsp_iq_buffer_ptr++ = 0;
2108
2109 if(iq_dump_buffer_log_index >= IQ_DUMP_BUFFER_SIZE){
2110 iq_overflow_ind=1;
2111 iq_dump_buffer_log_index = 0;
2112 }
2113
2114 iq_dump_buffer[iq_dump_buffer_log_index].task = task;
2115 iq_dump_buffer[iq_dump_buffer_log_index].hole = 0;
2116 iq_dump_buffer[iq_dump_buffer_log_index].size = size;
2117 iq_dump_buffer[iq_dump_buffer_log_index].fn_mod42432 = l1s.actual_time.fn_mod42432;
2118
2119 memcpy(&iq_dump_buffer[iq_dump_buffer_log_index].iq_sample[0],
2120 p_dsp_iq_buffer_ptr,
2121 size*2*2); /* size * 2 (as size is in IQsample pair) * 2 (to convert to bytes) */
2122
2123 iq_dump_buffer_log_index = iq_dump_buffer_log_index + 1;
2124 }
2125 #endif