FreeCalypso > hg > fc-tourmaline

annotate src/cs/drivers/drv_core/timer/timer2.h @ 75:8697f358f505

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backlight rework: Condat light driver accepts levels The present change is another intermediate step on the path toward new FreeCalypso backlight handling. At this intermediate step the Condat light driver accepts 0-255 backlight levels driven by MFW, and puts them out on PWL on Luna development boards. At the same time on C139 it is now possible to turn on the display backlight with or without the keypad bl - the lsb of the 0-255 backlight level controls the keypad bl. MFW presently drives only 0 and 255 backlight levels, thus there is no visible behavioral change yet - but the plan for subsequent stages of this backlight rework is to add a dimmed backlight state (no keypad bl on C139) during active calls.
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 24 Oct 2020 20:44:04 +0000
parents 4e78acac3d88
children
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /*******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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11 Filename : timer2.h
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13 Description :TIMER1
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15 Project : drivers
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17 Author : pmonteil@tif.ti.com Patrice Monteil.
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19 Version number : 1.4
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21 Date and time : 02/15/01 15:47:05
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23 Previous delta : 02/15/01 15:47:05
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED/drivers1/common/SCCS/s.timer2.h
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27 Sccs Id (SID) : '@(#) timer2.h 1.4 02/15/01 15:47:05 '
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31 *****************************************************************************/
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33 #include "l1sw.cfg"
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35 #if (OP_L1_STANDALONE == 0)
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36 #include "main/sys_types.h"
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37 #else
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38 #include "sys_types.h"
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39 #endif
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42 /**** DIONE TIMERs configuration register ****/
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44 #define D_TIMER_ADDR 0xfffe6800
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46 #define D_TIMER_CNTL_MASK 0x001f
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48 #define CNTL_D_TIMER_OFFSET 0x0000
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49 #define LOAD_D_TIMER_OFFSET 0x0002
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50 #define READ_D_TIMER_OFFSET 0x0004
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52 #define D_TIMER_CNTL (D_TIMER_ADDR+CNTL_D_TIMER_OFFSET)
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53 #define D_TIMER_LOAD (D_TIMER_ADDR+LOAD_D_TIMER_OFFSET)
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54 #define D_TIMER_READ (D_TIMER_ADDR+READ_D_TIMER_OFFSET)
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56 #define D_TIMER_ST 0x0001 /* bit 0 */
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57 #define D_TIMER_AR 0x0002 /* bit 1 */
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58 #define D_TIMER_PTV 0x001c /* bits 4:2 */
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59 #define D_TIMER_CLK_EN 0x0020 /* bit 5 */
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60 #define D_TIMER_RUN 0x0021 /* bit 5 ,0 */
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62 #define LOAD_TIM 0xffff /* bits 15:0 */
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68 /* ----- Prototypes ----- */
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69 SYS_UWORD16 Dtimer2_Get_cntlreg(void);
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71 void Dtimer2_AR(SYS_UWORD16 Ar);
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73 void Dtimer2_PTV(SYS_UWORD16 Ptv);
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75 void Dtimer2_Clken(SYS_UWORD16 En);
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77 void Dtimer2_Start (SYS_UWORD16 startStop);
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79 void Dtimer2_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
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81 void Dtimer2_WriteValue (SYS_UWORD16 value);
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83 SYS_UWORD16 Dtimer2_ReadValue (void);