FreeCalypso > hg > fc-tourmaline

annotate src/cs/drivers/drv_core/armio/armio.h @ 273:5caa86ee2cfa

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enable L1_NEW_AEC in l1_confg.h (bold change) The AEC function implemented in DSP ROM 3606 on the Calypso silicon we work with is the one that corresponds to L1_NEW_AEC; the same holds for DSP 34 and even for DSP 33 with more recent patch versions. However, TI shipped their TCS211 reference fw with L1_NEW_AEC set to 0, thus driving AEC the old way if anyone tried to enable it, either via AT%Nxxxx or via the audio mode facility. As a result, the fw would try to control features which no longer exist in the DSP (long vs short echo and the old echo suppression level bits), while providing no way to tune the 8 new parameter words added to the DSP's NDB page. The only sensible solution is to bite the bullet and enable L1_NEW_AEC in L1 config, with fallout propagating into RiViera Audio Service T_AUDIO_AEC_CFG structure and into /aud/*.cfg binary file format. The latter fallout will be addressed in further code changes.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 29 Jul 2021 18:32:40 +0000
parents 4e78acac3d88
children
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /*
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2 * ARMIO.H * * Control diagnostic bits * * Reference : GCS207 *
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3 */
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4
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5 #include "chipset.cfg"
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6
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7 #include "l1sw.cfg"
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8
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9 #if (OP_L1_STANDALONE == 0)
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10 #include "main/sys_types.h"
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11 #else
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12 #include "sys_types.h"
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13 #endif
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14
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15
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16 // Duplicate address with ARMIO_IO_CNTL
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17 // Need to investigate !!!
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18 //#define ARMIO_CNTL (MEM_ARMIO + 0x04) /* I/O control */
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19
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20 #define ARMIO_IN (MEM_ARMIO + 0x00) /* inputs */
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21 #define ARMIO_OUT (MEM_ARMIO + 0x02) /* outputs */
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22 #define ARMIO_IO_CNTL (MEM_ARMIO + 0x04) /* I/O control */
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23 #define ARMIO_CNTL_REG (MEM_ARMIO + 0x06) /* control ARMIO */
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24 #define ARMIO_LOAD_TIM (MEM_ARMIO + 0x08) /* load TIM */
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25 #if (CHIPSET != 12)
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26 #define ARMIO_KBR_IN (MEM_ARMIO + 0x0A) /* KBR inputs (rows) */
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27 #define ARMIO_KBR_OUT (MEM_ARMIO + 0x0C) /* KBR outputs (columns) */
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28 #endif
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29 #define ARMIO_PWM_CNTL (MEM_ARMIO + 0x0E) /* LIGHT/BUZZER control */
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30 #define ARMIO_LIGHT (MEM_ARMIO + 0x10) /* light value */
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31 #define ARMIO_BUZZER (MEM_ARMIO + 0x12) /* buzzer value */
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32 #define ARMIO_CLOCKEN 0x0020
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33 #if (CHIPSET != 12)
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34 #define CLKM_IO_CNTL MEM_IO_SEL /* control IO */
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35 #endif
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36
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37 #if (CHIPSET == 12)
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38 #define GPIO_INTERRUPT_LEVEL_REG * (volatile SYS_UWORD16 *) (MEM_ARMIO + 0x16)
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39 #define GPIO_INTERRUPT_MASK_REG * (volatile SYS_UWORD16 *) (MEM_ARMIO + 0x18)
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40 #else
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41 #define ARMIO_GPIO_EVENT_MODE (MEM_ARMIO + 0x14) /* GPIO event mode */
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42 #define ARMIO_KBD_GPIO_INT (MEM_ARMIO + 0x16) /* Kbd/GPIO IRQ register */
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43 #define ARMIO_KBD_GPIO_MASKIT (MEM_ARMIO + 0x18) /* Kbd/GPIO mask IRQ */
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44 // CC test 0316
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45 #define ARMIO_GPIO_DEBOUNCE (MEM_ARMIO + 0x1A) /* GPIO debounceing register*/
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46 // end
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47 #endif
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48
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49
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50 #if (CHIPSET != 12)
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51 #define ARMIO_DCD (2) /* IO used for DCD on C-Sample - Output */
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52 #endif
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53 #define ARMIO_DTR (3) /* IO used for DTR on C-Sample - Input */
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54
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55 #define ARMIO_FALLING_EDGE (0)
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56 #define ARMIO_RISING_EDGE (1)
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57
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58 #if (CHIPSET != 12)
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59 #define ARMIO_KEYPDAD_INT (0x0001)
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60 #define ARMIO_GPIO_INT (0x0002)
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61
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62 #define ARMIO_MASKIT_KBD (0x0001)
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63 #define ARMIO_MASKIT_GPIO (0x0002)
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64
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65 void AI_EnableBit(int bit);
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66 void AI_DisableBit(int bit);
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67 #endif
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68 void AI_SetBit(int bit);
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69 void AI_ResetBit(int bit);
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70 void AI_ConfigBitAsOutput(int bit);
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71 void AI_ConfigBitAsInput(int bit);
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72 SYS_BOOL AI_ReadBit(int bit);
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73 void AI_SetSimIO3V(SYS_UWORD8 StdOutput);
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74
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75 #if (OP_L1_STANDALONE == 0)
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76 void AI_Power(SYS_UWORD8 power);
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77 #endif
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78
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79 void AI_ResetTspIO(void);
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80 void AI_ResetDbgReg(void);
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81 void AI_ResetIoConfig(void);
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82 void AI_InitIOConfig(void);
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83 void AI_ClockEnable (void);
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84
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85 void AI_SelectIOForIT (SYS_UWORD16 Pin, SYS_UWORD16 Edge);
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86 #if (CHIPSET != 12)
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87 int AI_CheckITSource (SYS_UWORD16 Source);
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88 #endif
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89 void AI_UnmaskIT (SYS_UWORD16 Source);
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90 void AI_MaskIT (SYS_UWORD16 Source);
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91