| Fri, 25 Jun 2021 22:52:20 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2.pcb complete except for DRC
   
   | 
 
 
  | Fri, 25 Jun 2021 22:31:24 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2.pcb almost complete
   
   | 
 
 
  | Fri, 25 Jun 2021 20:29:36 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2.pcb started
   
   | 
 
 
  | Fri, 25 Jun 2021 19:11:21 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2/src/Makefile: generate elements.pcb
   
   | 
 
 
  | Fri, 25 Jun 2021 19:08:13 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2/src/Makefile: generate pcb-netlist.txt
   
   | 
 
 
  | Fri, 25 Jun 2021 19:01:35 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2: MCL binding complete
   
   | 
 
 
  | Fri, 25 Jun 2021 18:44:11 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2: structural Verilog source captured
   
   | 
 
 
  | Fri, 25 Jun 2021 17:12:02 +0000 | 
  Mychaela Falconia | 
  
   lunalcd2: footprint for the DIP switch pack
   
   |