https://www.freecalypso.org/hg/fc-small-hw/ en-us fc-small-hw: lunalcd2/src/Makefile history lunalcd2/src/Makefile revision history lunalcd2/src/Makefile: generate BOM outputs https://www.freecalypso.org/hg/fc-small-hw/log/000411b39576/lunalcd2/src/Makefile Mychaela Falconia <falcon@freecalypso.org> Sat, 26 Jun 2021 21:16:48 +0000 lunalcd2/src/Makefile: generate elements.pcb https://www.freecalypso.org/hg/fc-small-hw/log/907bff95244d/lunalcd2/src/Makefile Mychaela Falconia <falcon@freecalypso.org> Fri, 25 Jun 2021 19:11:21 +0000 lunalcd2/src/Makefile: generate pcb-netlist.txt https://www.freecalypso.org/hg/fc-small-hw/log/df8f40386c0b/lunalcd2/src/Makefile Mychaela Falconia <falcon@freecalypso.org> Fri, 25 Jun 2021 19:08:13 +0000 lunalcd2: MCL binding complete https://www.freecalypso.org/hg/fc-small-hw/log/38c713964bb7/lunalcd2/src/Makefile Mychaela Falconia <falcon@freecalypso.org> Fri, 25 Jun 2021 19:01:35 +0000 lunalcd2: structural Verilog source captured https://www.freecalypso.org/hg/fc-small-hw/log/d5d14b426faa/lunalcd2/src/Makefile Mychaela Falconia <falcon@freecalypso.org> Fri, 25 Jun 2021 18:44:11 +0000