# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1624646651 0
# Node ID d5d14b426faaf2e735d63e01964baaeff68be053
# Parent  99328e0ff61a04b22c62dea00dc4c46f53de4193
lunalcd2: structural Verilog source captured

diff -r 99328e0ff61a -r d5d14b426faa lunalcd2/src/Makefile
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/Makefile	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,11 @@
+VSRCS=	vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \
+	vsrc/current_select.v vsrc/lcd_module.v
+NETS=	sverp.unet
+
+all:	${NETS}
+
+sverp.unet:	${VSRCS} primitives Makefile
+	ueda-sverp -o $@ ${VSRCS}
+
+clean:
+	rm -f *.unet *.txt *.csv errs elements.pcb
diff -r 99328e0ff61a -r d5d14b426faa lunalcd2/src/primitives
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/primitives	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,16 @@
+/* passives */
+resistor	numpins 2;
+capacitor	numpins 2;
+
+/* LCD module */
+lcd_module_fp	numpins 36;
+
+/* MAX1916 IC */
+pkg_SOT23_6	numpins 6;
+
+/* DIP switch pack */
+pkg_DIP_SW_x4	numpins 8;
+
+/* connectors */
+header_2pin	numpins 2;
+header_26pin	numpins 26;
diff -r 99328e0ff61a -r d5d14b426faa lunalcd2/src/vsrc/MAX1916.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/MAX1916.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,16 @@
+module MAX1916 (GND, EN, SET, LEDK);
+
+input GND, EN, SET;
+output [1:3] LEDK;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_SOT23_6 pkg (.pin_1(EN),
+		 .pin_2(GND),
+		 .pin_3(SET),
+		 .pin_4(LEDK[3]),
+		 .pin_5(LEDK[2]),
+		 .pin_6(LEDK[1])
+	);
+
+endmodule
diff -r 99328e0ff61a -r d5d14b426faa lunalcd2/src/vsrc/bl_current_sink.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/bl_current_sink.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,18 @@
+module bl_current_sink (GND, Vio, BL_EN, LEDK);
+
+input GND, Vio, BL_EN;
+output [1:3] LEDK;
+
+wire SET;
+
+MAX1916 MAX1916 (.GND(GND),
+		 .EN(BL_EN),
+		 .SET(SET),
+		 .LEDK(LEDK)
+	);
+
+current_select cursel ( .Vio(Vio),
+			.SET(SET)
+	);
+
+endmodule
diff -r 99328e0ff61a -r d5d14b426faa lunalcd2/src/vsrc/board.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/board.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,78 @@
+module board ();
+
+wire GND, VBAT, Vio, Vio_LCD;
+wire [15:0] DB;
+wire RD, WR, RS, CS, RESET;
+wire BL_EN;
+wire [1:3] LEDK;	/* 1=left, 2=middle, 3=right for layout */
+
+/* main interface connector */
+
+header_26pin main_if (  .pin_1(DB[15]),
+			.pin_2(DB[14]),
+			.pin_3(DB[13]),
+			.pin_4(DB[12]),
+			.pin_5(DB[11]),
+			.pin_6(DB[10]),
+			.pin_7(DB[9]),
+			.pin_8(DB[8]),
+			.pin_9(DB[7]),
+			.pin_10(DB[6]),
+			.pin_11(DB[5]),
+			.pin_12(DB[4]),
+			.pin_13(DB[3]),
+			.pin_14(DB[2]),
+			.pin_15(DB[1]),
+			.pin_16(DB[0]),
+			.pin_17(CS),
+			.pin_18(RD),
+			.pin_19(WR),
+			.pin_20(RS),
+			.pin_21(GND),
+			.pin_22(GND),
+			.pin_23(RESET),
+			.pin_24(Vio),
+			.pin_25(BL_EN),
+			.pin_26(GND)
+	);
+
+resistor BL_EN_pulldown (BL_EN, GND);
+
+/* backlight power supply */
+
+header_2pin VBAT_conn ( .pin_1(VBAT),
+			.pin_2(GND)
+	);
+
+/* LCD module */
+
+resistor LCD_current_meas (Vio, Vio_LCD);
+
+capacitor LCD_bypass_cap (Vio_LCD, GND);
+
+lcd_module lcd (.GND(GND),
+		.VCI(Vio_LCD),
+		.IOVCC(Vio_LCD),
+		.DB(DB),
+		.RD(RD),
+		.WR(WR),
+		.RS(RS),
+		.CS(CS),
+		.RESET(RESET),
+		.IM0(GND),
+		.LEDA(VBAT),
+		/* LEDK order for layout */
+		.LEDK[1](LEDK[3]),
+		.LEDK[2](LEDK[2]),
+		.LEDK[3](LEDK[1])
+	);
+
+/* MAX1916-based backlight LED current sink */
+
+bl_current_sink bl_current_sink (.GND(GND),
+				 .Vio(Vio),
+				 .BL_EN(BL_EN),
+				 .LEDK(LEDK)
+	);
+
+endmodule
diff -r 99328e0ff61a -r d5d14b426faa lunalcd2/src/vsrc/current_select.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/current_select.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,23 @@
+module current_select (Vio, SET);
+
+input Vio;
+output SET;
+
+wire sw_1mA, sw_2mA, sw_4mA, sw_8mA;
+
+pkg_DIP_SW_x4 dipsw (	.pin_1(Vio),
+			.pin_2(sw_8mA),
+			.pin_3(Vio),
+			.pin_4(sw_4mA),
+			.pin_5(Vio),
+			.pin_6(sw_2mA),
+			.pin_7(Vio),
+			.pin_8(sw_1mA)
+	);
+
+resistor R_1mA (sw_1mA, SET);
+resistor R_2mA (sw_2mA, SET);
+resistor R_4mA (sw_4mA, SET);
+resistor R_8mA (sw_8mA, SET);
+
+endmodule
diff -r 99328e0ff61a -r d5d14b426faa lunalcd2/src/vsrc/lcd_module.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/lcd_module.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,50 @@
+module lcd_module (GND, VCI, IOVCC, DB, RD, WR, RS, CS, RESET, IM0, LEDA, LEDK);
+
+input GND, VCI, IOVCC;
+inout [15:0] DB;
+input RD, WR, RS, CS, RESET, IM0;
+input LEDA;
+input [1:3] LEDK;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+lcd_module_fp pkg (.pin_1(DB[15]),
+		   .pin_2(DB[14]),
+		   .pin_3(DB[13]),
+		   .pin_4(DB[12]),
+		   .pin_5(DB[11]),
+		   .pin_6(DB[10]),
+		   .pin_7(DB[9]),
+		   .pin_8(DB[8]),
+		   .pin_9(GND),
+		   .pin_10(DB[7]),
+		   .pin_11(DB[6]),
+		   .pin_12(DB[5]),
+		   .pin_13(DB[4]),
+		   .pin_14(DB[3]),
+		   .pin_15(DB[2]),
+		   .pin_16(DB[1]),
+		   .pin_17(DB[0]),
+		   .pin_18(IOVCC),
+		   .pin_19(VCI),
+		   .pin_20(RD),
+		   .pin_21(WR),
+		   .pin_22(RS),
+		   .pin_23(CS),
+		   .pin_24(RESET),
+		   .pin_25(IM0),
+		   .pin_26(GND),
+		   .pin_27(LEDA),
+		   .pin_28(LEDK[1]),
+		   .pin_29(LEDK[2]),
+		   .pin_30(LEDK[3]),
+		   /* the remaining pins are NC */
+		   .pin_31(),
+		   .pin_32(),
+		   .pin_33(),
+		   .pin_34(),
+		   .pin_35(),
+		   .pin_36()
+	);
+
+endmodule