# HG changeset patch # User Mychaela Falconia # Date 1593381984 0 # Node ID bd7eec55ebc0dcbbe97c12b71b27f6ce3e9ba068 # Parent b58388f57c16146bddd190e96e8fcaed07229bee duart28: new design ideas * added input buffers (LVC with Ioff feature) to prevent high current flow from powered-up target into powered-down FT2232D inputs; * added series resistors on outputs to limit current flow from powered-up adapter into powered-down Calypso target; * buffer IC changed from 74LVC125A to 74LVC541A. diff -r b58388f57c16 -r bd7eec55ebc0 duart28/src/MCL --- a/duart28/src/MCL Sat Jun 13 18:12:28 2020 +0000 +++ b/duart28/src/MCL Sun Jun 28 22:06:24 2020 +0000 @@ -99,16 +99,23 @@ footprint=file:TLV702xxDBV npins=5 +part 74LVC541A: + device=74LVC541A + manufacturer=Nexperia + manufacturer_part_number=74LVC541APW + description=Octal buffer IC, TSSOP20 package + vendor=Digi-Key + vendor_part_number=1727-6370-1-ND + footprint=file:TSSOP20_MNF + npins=20 + # buffer for driving outputs from the adapter U5: - device=74LVC125A - manufacturer=Nexperia - manufacturer_part_number=74LVC125APW - description=Quad buffer IC, TSSOP14 package - vendor=Digi-Key - vendor_part_number=1727-2868-ND - footprint=file:TSSOP14_MNF - npins=14 + part=74LVC541A + +# buffer for inputs coming into the adapter +U6: + part=74LVC541A # Crystal diff -r b58388f57c16 -r bd7eec55ebc0 duart28/src/primitives --- a/duart28/src/primitives Sat Jun 13 18:12:28 2020 +0000 +++ b/duart28/src/primitives Sun Jun 28 22:06:24 2020 +0000 @@ -13,9 +13,9 @@ pkg_5pin numpins 5; pkg_8pin numpins 8; -/* 74LVC125A single buffer and common part subpackages */ -buffer_ic_slot mapped_pins (A, Y, nOE); -buffer_ic_common mapped_pins (Vcc, GND); +/* 74LVC541A single buffer and common part subpackages */ +buffer_ic_slot mapped_pins (A, Y); +buffer_ic_common mapped_pins (Vcc, GND, nOE1, nOE2); /* crystal resonator */ xtal_2pin_pkg numpins 2; diff -r b58388f57c16 -r bd7eec55ebc0 duart28/src/vsrc/application_block.v --- a/duart28/src/vsrc/application_block.v Sat Jun 13 18:12:28 2020 +0000 +++ b/duart28/src/vsrc/application_block.v Sun Jun 28 22:06:24 2020 +0000 @@ -3,39 +3,90 @@ * dual UART with 2.8V outputs. */ -module application_block (GND, P_2V8, ADBUS, BDBUS); +module application_block (GND, P_3V3, P_2V8, ADBUS, BDBUS); -input GND, P_2V8; +input GND, P_3V3, P_2V8; inout [7:0] ADBUS, BDBUS; /* 2.8V output wires */ -wire TxD_2V8, RTS_2V8, DTR_2V8, TxD2_2V8; +wire TxD_2V8_before_R, RTS_2V8_before_R, DTR_2V8_before_R, TxD2_2V8_before_R; +wire TxD_2V8_after_R, RTS_2V8_after_R, DTR_2V8_after_R, TxD2_2V8_after_R; + +/* input signal wires */ + +wire RxD_in, CTS_in, DSR_in, DCD_in, RI_in, RxD2_in; /* output buffers */ -buffer_ic_common output_buf_common (.Vcc(P_2V8), .GND(GND)); +buffer_ic_common output_buf_common (.Vcc(P_2V8), + .GND(GND), + .nOE1(GND), + .nOE2(GND) + ); + capacitor output_buf_bypass_cap (P_2V8, GND); -buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8), .nOE(GND)); -buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8), .nOE(GND)); -buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8), .nOE(GND)); -buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8), .nOE(GND)); +buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8_before_R)); +buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8_before_R)); +buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8_before_R)); +buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8_before_R)); + +buffer_ic_slot unused_output_buf1 (.A(GND), .Y()); +buffer_ic_slot unused_output_buf2 (.A(GND), .Y()); +buffer_ic_slot unused_output_buf3 (.A(GND), .Y()); +buffer_ic_slot unused_output_buf4 (.A(GND), .Y()); + +/* output series resistors */ + +resistor TxD_series_R (TxD_2V8_before_R, TxD_2V8_after_R); +resistor RTS_series_R (RTS_2V8_before_R, RTS_2V8_after_R); +resistor DTR_series_R (DTR_2V8_before_R, DTR_2V8_after_R); +resistor TxD2_series_R (TxD2_2V8_before_R, TxD2_2V8_after_R); + +/* input buffers */ + +buffer_ic_common input_buf_common (.Vcc(P_3V3), + .GND(GND), + .nOE1(GND), + .nOE2(GND) + ); + +capacitor input_buf_bypass_cap (P_3V3, GND); + +buffer_ic_slot buf_RxD (.A(RxD_in), .Y(ADBUS[1])); +buffer_ic_slot buf_CTS (.A(CTS_in), .Y(ADBUS[3])); +buffer_ic_slot buf_DSR (.A(DSR_in), .Y(ADBUS[5])); +buffer_ic_slot buf_DCD (.A(DCD_in), .Y(ADBUS[6])); +buffer_ic_slot buf_RI (.A(RI_in), .Y(ADBUS[7])); +buffer_ic_slot buf_RxD2 (.A(RxD2_in), .Y(BDBUS[1])); + +buffer_ic_slot unused_input_buf1 (.A(GND), .Y()); +buffer_ic_slot unused_input_buf2 (.A(GND), .Y()); + +/* input pull-up resistors */ + +resistor RxD_pullup (RxD_in, P_2V8); +resistor CTS_pullup (CTS_in, P_2V8); +resistor DSR_pullup (DSR_in, P_2V8); +resistor DCD_pullup (DCD_in, P_2V8); +resistor RI_pullup (RI_in, P_2V8); +resistor RxD2_pullup (RxD2_in, P_2V8); /* target interface headers */ target_if target_if ( .GND(GND), - .UART0_TxD(TxD_2V8), - .UART0_RxD(ADBUS[1]), - .UART0_RTS(RTS_2V8), - .UART0_CTS(ADBUS[3]), - .UART0_DTR(DTR_2V8), - .UART0_DSR(ADBUS[5]), - .UART0_DCD(ADBUS[6]), - .UART0_RI(ADBUS[7]), - .UART1_TxD(TxD2_2V8), - .UART1_RxD(BDBUS[1]) + .UART0_TxD(TxD_2V8_after_R), + .UART0_RxD(RxD_in), + .UART0_RTS(RTS_2V8_after_R), + .UART0_CTS(CTS_in), + .UART0_DTR(DTR_2V8_after_R), + .UART0_DSR(DSR_in), + .UART0_DCD(DCD_in), + .UART0_RI(RI_in), + .UART1_TxD(TxD2_2V8_after_R), + .UART1_RxD(RxD2_in) ); endmodule diff -r b58388f57c16 -r bd7eec55ebc0 duart28/src/vsrc/board.v --- a/duart28/src/vsrc/board.v Sat Jun 13 18:12:28 2020 +0000 +++ b/duart28/src/vsrc/board.v Sun Jun 28 22:06:24 2020 +0000 @@ -22,6 +22,7 @@ regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8)); application_block app ( .GND(GND), + .P_3V3(P_3V3), .P_2V8(P_2V8), .ADBUS(ADBUS), .BDBUS(BDBUS)