# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1596009560 0
# Node ID 5bdd24aae51e83e6b0db16edc1e5958916c335ba
# Parent  d4da3aed4c1e732eb12e520e3bb4b4db2133cd24
duart28c: new parts added to netlist

diff -r d4da3aed4c1e -r 5bdd24aae51e duart28c/src/MCL
--- a/duart28c/src/MCL	Wed Jul 29 07:30:45 2020 +0000
+++ b/duart28c/src/MCL	Wed Jul 29 07:59:20 2020 +0000
@@ -102,6 +102,7 @@
 
 C16:
  # bypass cap for new 74LVC2G07 IC
+ hier=app.bctl.od_buf_bypass_cap
  part=0603C-X7R-100nF
 
 # Connectors
@@ -157,6 +158,7 @@
 
 # boot control OD outputs
 J5:
+ hier=app.bctl.ctl_if
  part=header-3pin
 
 # Ferrite bead
@@ -299,10 +301,12 @@
 
 R17:
  # pull-up on BDBUS2
+ hier=app.bctl.ChanB_RTS_pullup
  part=0402R-100k
 
 R18:
  # pull-up on BDBUS4
+ hier=app.bctl.ChanB_DTR_pullup
  part=0402R-100k
 
 # ICs
@@ -378,6 +382,7 @@
  vendor=Digi-Key
  vendor_part_number=1727-7008-1-ND
  pinout=74LVC2G07.pinout
+ slotmap=U7.slotmap
  npins=6
 
 # Crystal
diff -r d4da3aed4c1e -r 5bdd24aae51e duart28c/src/Makefile
--- a/duart28c/src/Makefile	Wed Jul 29 07:30:45 2020 +0000
+++ b/duart28c/src/Makefile	Wed Jul 29 07:59:20 2020 +0000
@@ -1,7 +1,7 @@
 VSRCS=	vsrc/FT2232D_block.v vsrc/FT2232D_chip.v vsrc/USB_block.v \
-	vsrc/application_block.v vsrc/board.v vsrc/eeprom_93Cx6_16bit.v \
-	vsrc/regulator_ic.v vsrc/regulator_with_caps.v vsrc/target_if.v \
-	vsrc/usb_conn.v
+	vsrc/application_block.v vsrc/board.v vsrc/boot_ctrl.v \
+	vsrc/eeprom_93Cx6_16bit.v vsrc/regulator_ic.v \
+	vsrc/regulator_with_caps.v vsrc/target_if.v vsrc/usb_conn.v
 BOMS=	tallied-bom.txt tallied-bom.csv comptab.txt
 NETS=	sverp.unet bound.unet pcb-netlist.txt
 
diff -r d4da3aed4c1e -r 5bdd24aae51e duart28c/src/U7.slotmap
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28c/src/U7.slotmap	Wed Jul 29 07:59:20 2020 +0000
@@ -0,0 +1,4 @@
+#instance		slot
+app.bctl.buf_CTL1	1
+app.bctl.buf_CTL2	2
+app.bctl.od_buf_common
diff -r d4da3aed4c1e -r 5bdd24aae51e duart28c/src/vsrc/application_block.v
--- a/duart28c/src/vsrc/application_block.v	Wed Jul 29 07:30:45 2020 +0000
+++ b/duart28c/src/vsrc/application_block.v	Wed Jul 29 07:59:20 2020 +0000
@@ -89,4 +89,12 @@
 			.UART1_RxD(RxD2_in)
 	);
 
+/* DUART28C boot control addition */
+
+boot_ctrl bctl (.GND(GND),
+		.P_3V3(P_3V3),
+		.ChanB_RTS(BDBUS[2]),
+		.ChanB_DTR(BDBUS[4])
+	);
+
 endmodule
diff -r d4da3aed4c1e -r 5bdd24aae51e duart28c/src/vsrc/boot_ctrl.v
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28c/src/vsrc/boot_ctrl.v	Wed Jul 29 07:59:20 2020 +0000
@@ -0,0 +1,35 @@
+/*
+ * This module encapsulates the boot control addition for DUART28C.
+ */
+
+module boot_ctrl (GND, P_3V3, ChanB_RTS, ChanB_DTR);
+
+input GND, P_3V3;
+input ChanB_RTS, ChanB_DTR;
+
+wire CTL1_out, CTL2_out;
+
+/* pull-up resistors on FT2232D outputs */
+
+resistor ChanB_RTS_pullup (ChanB_RTS, P_3V3);
+resistor ChanB_DTR_pullup (ChanB_DTR, P_3V3);
+
+/* open drain buffers */
+
+od_buffer_ic_common od_buf_common (.Vcc(P_3V3),
+				   .GND(GND)
+	);
+
+capacitor od_buf_bypass_cap (P_3V3, GND);
+
+od_buffer_ic_slot buf_CTL1 (.A(ChanB_RTS), .Y(CTL1_out));
+od_buffer_ic_slot buf_CTL2 (.A(ChanB_DTR), .Y(CTL2_out));
+
+/* header connector */
+
+header_3pin ctl_if (.pin_1(GND),
+		    .pin_2(CTL1_out),
+		    .pin_3(CTL2_out)
+	);
+
+endmodule