# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1595487572 0
# Node ID 40e2106a0500b598033b12088e854dd2bb6275f8
# Parent  846ebd21db8eb5ad799039644fd47c607f8d98c5
duart28/design-spec: coming along

diff -r 846ebd21db8e -r 40e2106a0500 duart28/design-spec
--- a/duart28/design-spec	Tue Jul 14 19:01:29 2020 +0000
+++ b/duart28/design-spec	Thu Jul 23 06:59:32 2020 +0000
@@ -180,3 +180,54 @@
 on, but no USB host) by inserting LVC buffers in front of FT2232D inputs -
 these LVC buffers are fully specified for partial power-down applications and
 have very small Ioff leakage current.
+
+2. Circuit design
+
+2.1. FT2232D core section
+
+Our FT2232D core section (basically everything from the USB connector to the
+FT2232D chip's ADBUS and BDBUS interfaces) is based on PLDkit's generic FT2232D
+module:
+
+ftp://ftp.freecalypso.org/pub/USB/FTDI/FT2232D_module_B_schematics.pdf
+
+This core section is essentially boilerplate in which we have zero desire for
+innovation, hence we would like to copy it from a known-working design.  In
+this project the section in question has been recaptured in our ueda language
+based on the above schematic drawing.
+
+2.2. UART outputs from the adapter
+
+We have a total of 4 outputs: TxD, RTS, DTR and TxD2.  Because we wish to put
+out 2.8V logic levels rather than 3.3V, each output needs to pass through an
+LVC buffer; we use a 74LVC541A as our buffer IC.
+
+There is also a series resistor inserted into each output after the LVC buffer;
+the initial value to be populated on the first board build is 2.2 kOhm, to be
+further tuned empirically.  The purpose of these series resistors is to limit
+the current that will flow from our DUART28 adapter into the Calypso target
+when the Calypso is powered down - see section 1.3.  In our current setup with
+direct FT2232D to Calypso connection (no series resistors) this current has
+been measured to be somewhere around 1.77 mA, and it appears to be limited by
+the current sourcing ability of FT2232D drivers (1 mA per datasheet).  However,
+our new LVC buffers have much stronger drivers, specified to both source and
+sink up to 24 mA, thus series resistors become mandatory for proper operation
+in this partial power-down scenario.
+
+The value of these series resistors is a delicate tuning job: they need to be
+large enough to limit current flow in the partial power-down scenario, but they
+cannot be too large, or they will adversely affect serial communication.  Each
+of these series resistors will form an RC circuit together with various
+parasitic capacitances on the Calypso target side; larger R translates to a
+larger RC time constant, resulting in slower signal rise and fall times,
+adversely affecting serial communication at higher baud rates.
+
+We have an existing Calypso development board produced by another company that
+features old-fashioned RS-232 interfaces (classic DE9F connectors) and uses an
+on-board RS-232 to LVTTL/LVCMOS converter; this board features 1 kOhm series
+resistors in the same place as in our proposed design, and it works fine at
+812500 baud.  If we populate the same 1 kOhm resistors, the undesirable current
+in the partial power-down scenario will be 2.8 mA per pin, which is greater
+than our current 1.77 mA; with our current plan of populating 2.2 kOhm resistors
+the current will be 1.27 mA, and we are hoping that 812500 baud communication
+will still work OK.