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comparison lunalcd2/src/vsrc/MAX1916.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
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58:99328e0ff61a 59:d5d14b426faa
1 module MAX1916 (GND, EN, SET, LEDK);
2
3 input GND, EN, SET;
4 output [1:3] LEDK;
5
6 /* instantiate the package; the mapping of signals to pins is defined here */
7
8 pkg_SOT23_6 pkg (.pin_1(EN),
9 .pin_2(GND),
10 .pin_3(SET),
11 .pin_4(LEDK[3]),
12 .pin_5(LEDK[2]),
13 .pin_6(LEDK[1])
14 );
15
16 endmodule