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comparison lunalcd2/src/primitives @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents lunalcd1/src/primitives@839e9b527e69
children
comparison
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58:99328e0ff61a 59:d5d14b426faa
1 /* passives */
2 resistor numpins 2;
3 capacitor numpins 2;
4
5 /* LCD module */
6 lcd_module_fp numpins 36;
7
8 /* MAX1916 IC */
9 pkg_SOT23_6 numpins 6;
10
11 /* DIP switch pack */
12 pkg_DIP_SW_x4 numpins 8;
13
14 /* connectors */
15 header_2pin numpins 2;
16 header_26pin numpins 26;