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comparison lunalcd2/src/Makefile @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
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children 38c713964bb7
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58:99328e0ff61a 59:d5d14b426faa
1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \
2 vsrc/current_select.v vsrc/lcd_module.v
3 NETS= sverp.unet
4
5 all: ${NETS}
6
7 sverp.unet: ${VSRCS} primitives Makefile
8 ueda-sverp -o $@ ${VSRCS}
9
10 clean:
11 rm -f *.unet *.txt *.csv errs elements.pcb