FreeCalypso > hg > fc-small-hw

comparison duart28/design-spec @ 35:846ebd21db8e

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
duart28/design-spec: minor fixes in the so-far-written section
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 14 Jul 2020 19:01:29 +0000
parents 0eca5449abd7
children 40e2106a0500
comparison
equal deleted inserted replaced
34:0eca5449abd7 35:846ebd21db8e
128 inputs; this arrangement has been working well for us since 2017, but a more 128 inputs; this arrangement has been working well for us since 2017, but a more
129 proper 2.8V DUART adapter is desirable for a few reasons: 129 proper 2.8V DUART adapter is desirable for a few reasons:
130 130
131 * When the Calypso+Iota chipset enters superdeep sleep (our shorthand term for 131 * When the Calypso+Iota chipset enters superdeep sleep (our shorthand term for
132 Calypso deep sleep combined with Iota ABB sleep mode), the chipset's VRIO 132 Calypso deep sleep combined with Iota ABB sleep mode), the chipset's VRIO
133 regulator (the one that produces the 2.8V V-IO raill) switches into sleep mode, 133 regulator (the one that produces the 2.8V V-IO rail) switches into sleep mode,
134 which has much looser regulation than in the regular Active mode. In this 134 which has much looser regulation than in the regular Active mode. In this
135 condition external 3.3V can feed into the V-IO rail through pull-up resistors 135 condition external 3.3V can feed into the V-IO rail through pull-up resistors
136 and pull the rail itself a little higher than where the chipset's own regulators 136 and pull the rail itself a little higher than where the chipset's own regulators
137 would have it, which is certainly not desirable. If UART inputs to the Calypso 137 would have it, which is certainly not desirable. If UART inputs to the Calypso
138 board are driven with 2.8V logic levels rather than 3.3V, this problem is not 138 board are driven with 2.8V logic levels rather than 3.3V, this problem is not
168 without putting LVC or similar buffers on the Calypso board side, but we need 168 without putting LVC or similar buffers on the Calypso board side, but we need
169 to be mindful of this current and we need to limit it. 169 to be mindful of this current and we need to limit it.
170 170
171 2) When a Calypso device is connected to the USB DUART adapter, the Calypso 171 2) When a Calypso device is connected to the USB DUART adapter, the Calypso
172 device is up and running (VRPC Active state), but there is no USB host 172 device is up and running (VRPC Active state), but there is no USB host
173 connected, current can flow from Calypso outputs into a powered-down FT2232D or 173 connected, current can flow from Calypso outputs into a powered-down FT2232D
174 other chips in the USB DUART adapter. With our current raw FT2232D-to-Calypso 174 (or other front-end chips) in the USB DUART adapter. With our current raw
175 arrangement we have about 5 mA of current flowing per pin under the described 175 FT2232D-to-Calypso arrangement we have about 5 mA of current flowing per pin
176 condition, which is a little too much. 176 under the described condition, which is a little too much.
177 177
178 If we replace the generic FT2232D breakout with our own custom adapter board 178 If we replace the generic FT2232D breakout with our own custom adapter board
179 design, we can solve the second partial power-down problem (the case of Calypso 179 design, we can solve the second partial power-down problem (the case of Calypso
180 on, but no USB host) by inserting LVC buffers in front of FT2232D inputs - 180 on, but no USB host) by inserting LVC buffers in front of FT2232D inputs -
181 these LVC buffers are fully specified for partial power-down applications and 181 these LVC buffers are fully specified for partial power-down applications and