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comparison duart28/src/primitives @ 22:43097651a26d

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duart28/src/primitives: adapted from fc-uja
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 05:28:01 +0000
parents
children bd7eec55ebc0
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21:dbcb1d02d256 22:43097651a26d
1 /*
2 * This file defines the primitives to be instantiated from the structural
3 * Verilog source for the board: IC package types, basic components and
4 * subpackages to be mapped later in the MCL binding step.
5 */
6
7 resistor numpins 2;
8 capacitor numpins 2;
9 inductor numpins 2;
10
11 /* IC packages */
12 pkg_LQFP48 numpins 48;
13 pkg_5pin numpins 5;
14 pkg_8pin numpins 8;
15
16 /* 74LVC125A single buffer and common part subpackages */
17 buffer_ic_slot mapped_pins (A, Y, nOE);
18 buffer_ic_common mapped_pins (Vcc, GND);
19
20 /* crystal resonator */
21 xtal_2pin_pkg numpins 2;
22
23 /* connectors */
24 header_2pin numpins 2;
25 header_3pin numpins 3;
26 header_10pin numpins 10;
27 conn_miniUSB_plus4 numpins 9;