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comparison duart28/src/vsrc/application_block.v @ 23:22aba3a61a4b

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duart28: vsrc passes sverp
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:38:05 +0000
parents
children bd7eec55ebc0
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22:43097651a26d 23:22aba3a61a4b
1 /*
2 * This module encapsulates the application function of our board:
3 * dual UART with 2.8V outputs.
4 */
5
6 module application_block (GND, P_2V8, ADBUS, BDBUS);
7
8 input GND, P_2V8;
9
10 inout [7:0] ADBUS, BDBUS;
11
12 /* 2.8V output wires */
13
14 wire TxD_2V8, RTS_2V8, DTR_2V8, TxD2_2V8;
15
16 /* output buffers */
17
18 buffer_ic_common output_buf_common (.Vcc(P_2V8), .GND(GND));
19 capacitor output_buf_bypass_cap (P_2V8, GND);
20
21 buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8), .nOE(GND));
22 buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8), .nOE(GND));
23 buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8), .nOE(GND));
24 buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8), .nOE(GND));
25
26 /* target interface headers */
27
28 target_if target_if ( .GND(GND),
29 .UART0_TxD(TxD_2V8),
30 .UART0_RxD(ADBUS[1]),
31 .UART0_RTS(RTS_2V8),
32 .UART0_CTS(ADBUS[3]),
33 .UART0_DTR(DTR_2V8),
34 .UART0_DSR(ADBUS[5]),
35 .UART0_DCD(ADBUS[6]),
36 .UART0_RI(ADBUS[7]),
37 .UART1_TxD(TxD2_2V8),
38 .UART1_RxD(BDBUS[1])
39 );
40
41 endmodule