FreeCalypso > hg > fc-small-hw

comparison duart28/src/vsrc/FT2232D_chip.v @ 23:22aba3a61a4b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
duart28: vsrc passes sverp
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:38:05 +0000
parents
children
comparison
equal deleted inserted replaced
22:43097651a26d 23:22aba3a61a4b
1 /*
2 * This module encapsulates the FT2232D chip and its pinout.
3 */
4
5 module FT2232D_chip (GND, AGND, VCC, AVCC, VCCIOA, VCCIOB, OUT_3V3,
6 USBDP, USBDM, EECS, EESK, EEDATA, RESET, RSTOUT, TEST, PWREN,
7 XTIN, XTOUT, ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB);
8
9 input GND, AGND, VCC, AVCC, VCCIOA, VCCIOB;
10 output OUT_3V3;
11
12 inout USBDP, USBDM;
13 output EECS, EESK;
14 inout EEDATA;
15
16 input RESET, TEST;
17 output RSTOUT, PWREN;
18
19 input XTIN;
20 output XTOUT;
21
22 inout [7:0] ADBUS, BDBUS;
23 inout [3:0] ACBUS, BCBUS;
24 input SI_WUA, SI_WUB;
25
26 /* instantiate the package; the mapping of signals to pins is defined here */
27
28 pkg_LQFP48 pkg (.pin_1(EESK),
29 .pin_2(EEDATA),
30 .pin_3(VCC),
31 .pin_4(RESET),
32 .pin_5(RSTOUT),
33 .pin_6(OUT_3V3),
34 .pin_7(USBDP),
35 .pin_8(USBDM),
36 .pin_9(GND),
37 .pin_10(SI_WUA),
38 .pin_11(ACBUS[3]),
39 .pin_12(ACBUS[2]),
40 .pin_13(ACBUS[1]),
41 .pin_14(VCCIOA),
42 .pin_15(ACBUS[0]),
43 .pin_16(ADBUS[7]),
44 .pin_17(ADBUS[6]),
45 .pin_18(GND),
46 .pin_19(ADBUS[5]),
47 .pin_20(ADBUS[4]),
48 .pin_21(ADBUS[3]),
49 .pin_22(ADBUS[2]),
50 .pin_23(ADBUS[1]),
51 .pin_24(ADBUS[0]),
52 .pin_25(GND),
53 .pin_26(SI_WUB),
54 .pin_27(BCBUS[3]),
55 .pin_28(BCBUS[2]),
56 .pin_29(BCBUS[1]),
57 .pin_30(BCBUS[0]),
58 .pin_31(VCCIOB),
59 .pin_32(BDBUS[7]),
60 .pin_33(BDBUS[6]),
61 .pin_34(GND),
62 .pin_35(BDBUS[5]),
63 .pin_36(BDBUS[4]),
64 .pin_37(BDBUS[3]),
65 .pin_38(BDBUS[2]),
66 .pin_39(BDBUS[1]),
67 .pin_40(BDBUS[0]),
68 .pin_41(PWREN),
69 .pin_42(VCC),
70 .pin_43(XTIN),
71 .pin_44(XTOUT),
72 .pin_45(AGND),
73 .pin_46(AVCC),
74 .pin_47(TEST),
75 .pin_48(EECS)
76 );
77
78 endmodule