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annotate duart28/src/vsrc/target_if.v @ 47:ba1450b0c956

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duart28c MCL: new components added
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 29 Jul 2020 07:21:04 +0000
parents 22aba3a61a4b
children
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1 /* This module captures our target interfaces. */
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2
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3 module target_if (GND, UART0_TxD, UART0_RxD, UART0_RTS, UART0_CTS,
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4 UART0_DTR, UART0_DSR, UART0_DCD, UART0_RI,
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5 UART1_TxD, UART1_RxD);
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6
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7 input GND;
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8
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9 input UART0_TxD, UART0_RTS, UART0_DTR;
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10 output UART0_RxD, UART0_CTS, UART0_DSR, UART0_DCD, UART0_RI;
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11
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12 input UART1_TxD;
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13 output UART1_RxD;
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14
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15 /* main DUART signal set header */
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16
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17 header_10pin main_if ( .pin_1(GND),
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18 .pin_2(GND),
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19 .pin_3(UART1_RxD),
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20 .pin_4(UART0_RxD),
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21 .pin_5(UART1_TxD),
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22 .pin_6(UART0_TxD),
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23 .pin_7(UART0_DCD),
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24 .pin_8(UART0_CTS),
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25 .pin_9(UART0_DTR),
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26 .pin_10(UART0_RTS)
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27 );
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28
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29 /* auxiliary DSR and RI */
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30
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31 header_3pin aux_if (.pin_1(GND),
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32 .pin_2(UART0_DSR),
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33 .pin_3(UART0_RI)
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34 );
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35
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36 endmodule