FreeCalypso > hg > fc-small-hw
annotate lunalcd2/src/Makefile @ 62:907bff95244d
lunalcd2/src/Makefile: generate elements.pcb
| author | Mychaela Falconia <falcon@freecalypso.org> | 
|---|---|
| date | Fri, 25 Jun 2021 19:11:21 +0000 | 
| parents | df8f40386c0b | 
| children | 000411b39576 | 
| rev | line source | 
|---|---|
| 59 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \ | 
| 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 2 vsrc/current_select.v vsrc/lcd_module.v | 
| 61 
df8f40386c0b
lunalcd2/src/Makefile: generate pcb-netlist.txt
 Mychaela Falconia <falcon@freecalypso.org> parents: 
60diff
changeset | 3 NETS= sverp.unet bound.unet pcb-netlist.txt | 
| 59 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 4 | 
| 62 
907bff95244d
lunalcd2/src/Makefile: generate elements.pcb
 Mychaela Falconia <falcon@freecalypso.org> parents: 
61diff
changeset | 5 all: ${NETS} elements.pcb | 
| 59 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 6 | 
| 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 7 sverp.unet: ${VSRCS} primitives Makefile | 
| 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 8 ueda-sverp -o $@ ${VSRCS} | 
| 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 9 | 
| 60 
38c713964bb7
lunalcd2: MCL binding complete
 Mychaela Falconia <falcon@freecalypso.org> parents: 
59diff
changeset | 10 bound.unet: MCL sverp.unet | 
| 
38c713964bb7
lunalcd2: MCL binding complete
 Mychaela Falconia <falcon@freecalypso.org> parents: 
59diff
changeset | 11 unet-bind -c sverp.unet $@ | 
| 
38c713964bb7
lunalcd2: MCL binding complete
 Mychaela Falconia <falcon@freecalypso.org> parents: 
59diff
changeset | 12 | 
| 61 
df8f40386c0b
lunalcd2/src/Makefile: generate pcb-netlist.txt
 Mychaela Falconia <falcon@freecalypso.org> parents: 
60diff
changeset | 13 pcb-netlist.txt: bound.unet | 
| 
df8f40386c0b
lunalcd2/src/Makefile: generate pcb-netlist.txt
 Mychaela Falconia <falcon@freecalypso.org> parents: 
60diff
changeset | 14 unet2pcb bound.unet $@ | 
| 
df8f40386c0b
lunalcd2/src/Makefile: generate pcb-netlist.txt
 Mychaela Falconia <falcon@freecalypso.org> parents: 
60diff
changeset | 15 | 
| 62 
907bff95244d
lunalcd2/src/Makefile: generate elements.pcb
 Mychaela Falconia <falcon@freecalypso.org> parents: 
61diff
changeset | 16 elements.pcb: MCL | 
| 
907bff95244d
lunalcd2/src/Makefile: generate elements.pcb
 Mychaela Falconia <falcon@freecalypso.org> parents: 
61diff
changeset | 17 ueda-getfps -ch | ueda-runm4 > $@ | 
| 
907bff95244d
lunalcd2/src/Makefile: generate elements.pcb
 Mychaela Falconia <falcon@freecalypso.org> parents: 
61diff
changeset | 18 | 
| 59 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 19 clean: | 
| 
d5d14b426faa
lunalcd2: structural Verilog source captured
 Mychaela Falconia <falcon@freecalypso.org> parents: diff
changeset | 20 rm -f *.unet *.txt *.csv errs elements.pcb | 
