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annotate duart28/src/vsrc/application_block.v @ 25:5809654a24f4

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duart28 MCL: beginning of hier= mapping
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:57:04 +0000
parents 22aba3a61a4b
children bd7eec55ebc0
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1 /*
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2 * This module encapsulates the application function of our board:
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3 * dual UART with 2.8V outputs.
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4 */
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5
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6 module application_block (GND, P_2V8, ADBUS, BDBUS);
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7
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8 input GND, P_2V8;
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9
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10 inout [7:0] ADBUS, BDBUS;
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12 /* 2.8V output wires */
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13
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14 wire TxD_2V8, RTS_2V8, DTR_2V8, TxD2_2V8;
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16 /* output buffers */
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18 buffer_ic_common output_buf_common (.Vcc(P_2V8), .GND(GND));
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19 capacitor output_buf_bypass_cap (P_2V8, GND);
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21 buffer_ic_slot buf_TxD (.A(ADBUS[0]), .Y(TxD_2V8), .nOE(GND));
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22 buffer_ic_slot buf_RTS (.A(ADBUS[2]), .Y(RTS_2V8), .nOE(GND));
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23 buffer_ic_slot buf_DTR (.A(ADBUS[4]), .Y(DTR_2V8), .nOE(GND));
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24 buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8), .nOE(GND));
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25
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26 /* target interface headers */
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27
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28 target_if target_if ( .GND(GND),
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29 .UART0_TxD(TxD_2V8),
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30 .UART0_RxD(ADBUS[1]),
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31 .UART0_RTS(RTS_2V8),
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32 .UART0_CTS(ADBUS[3]),
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33 .UART0_DTR(DTR_2V8),
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34 .UART0_DSR(ADBUS[5]),
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35 .UART0_DCD(ADBUS[6]),
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36 .UART0_RI(ADBUS[7]),
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37 .UART1_TxD(TxD2_2V8),
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38 .UART1_RxD(BDBUS[1])
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39 );
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40
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41 endmodule