/*
 * This Verilog module captures the logic that detects rising edges of SIM_CLK
 * for the purpose of counting them.
 */

module clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);

input IntClk;
input SIM_CLK_sync;
output SIM_CLK_edge;

reg prev_state;

always @(posedge IntClk)
	prev_state <= SIM_CLK_sync;

assign SIM_CLK_edge = SIM_CLK_sync && !prev_state;

endmodule