/*
 * This Verilog module captures the logic that detects SIM_RST transitions
 * in either direction.
 */

module reset_detect (IntClk, SIM_RST_sync, SIM_RST_toggle);

input IntClk;
input SIM_RST_sync;
output SIM_RST_toggle;

reg prev_state;

always @(posedge IntClk)
	prev_state <= SIM_RST_sync;

assign SIM_RST_toggle = SIM_RST_sync != prev_state;

endmodule