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doc/PPS-catcher-FSM: initial description
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 22 Aug 2023 08:55:33 +0000
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children c2fc75655937
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23:abb72a74f27a 24:f1e7795557b1
1 This document describes the PPS catcher state machine (to be implemented in the
2 sniffer FPGA) in verbal pseudocode.
3
4 INITIAL:
5
6 This state will be entered upon reset (held in this state while RST is low).
7 Must receive 8'h3B to proceed to state T0, otherwise transition to DONE.
8
9 ATR_T0:
10
11 Whatever byte we receive in this state, we latch the upper nibble in the Y
12 register and the lower nibble in the K register - then proceed to TAn.
13
14 ATR_TAn:
15
16 Advance to TBn if Y register indicates no TAn OR we got a byte.
17
18 ATR_TBn:
19
20 Advance to TCn if Y register indicates no TBn OR we got a byte.
21
22 ATR_TCn:
23
24 Advance to TDn if Y register indicates no TCn OR we got a byte.
25
26 ATR_TDn:
27
28 If Y register indicates no TDn, advance to state ATR_HIST.
29
30 ELSE wait for byte; upon byte Rx, do the following:
31
32 - latch the upper nibble in the Y register;
33 - if lower nibble != 0, set TCK present flag;
34 - always go back to TAn.
35
36 ATR_HIST:
37
38 If K == 0, advance to state ATR_TCK.
39
40 ELSE wait for byte; upon byte Rx, decrement K and remain in this state.
41
42 ATR_TCK:
43
44 Advance to READY_FOR_PPS if Have_TCK flag is false OR we got a byte.
45
46 READY_FOR_PPS:
47
48 Wait for Rx byte. If the byte equals 8'hFF, proceed to REQ_PPS0,
49 otherwise DONE.
50
51 REQ_PPS0:
52
53 Wait for Rx byte; latch 3 bits of the received byte and proceed to REQ_PPS1.
54
55 REQ_PPS1:
56
57 Advance to REQ_PPS2 if register indicates no PPS1 OR we got a byte.
58
59 REQ_PPS2:
60
61 Advance to REQ_PPS3 if register indicates no PPS2 OR we got a byte.
62
63 REQ_PPS3:
64
65 Advance to REQ_PCK if register indicates no PPS3 OR we got a byte.
66
67 REQ_PCK:
68
69 Wait for Rx byte; ignore the received value and go to READY_FOR_RESP.
70
71 READY_FOR_RESP:
72
73 Wait for Rx byte. If the byte equals 8'hFF, proceed to RESP_PPS0,
74 otherwise DONE.
75
76 RESP_PPS0:
77
78 Wait for Rx byte. If PPS1 indicator bit is cleared, go to DONE. Otherwise,
79 latch the 3 bits like in REQ_PPS0 and proceed to RESP_PPS1.
80
81 RESP_PPS1:
82
83 Wait for Rx byte. The upper 6 bits must match 6'b100101 - if mismatch, go to
84 DONE. If the upper bits match, latch the two lsbs - they will be the speed
85 enhancement multiplier bits - and proceed to RESP_PPS2.
86
87 RESP_PPS2:
88
89 Advance to RESP_PPS3 if register indicates no PPS2 OR we got a byte.
90
91 RESP_PPS3:
92
93 Advance to RESP_PCK if register indicates no PPS3 OR we got a byte.
94
95 RESP_PCK:
96
97 Wait for Rx byte. Upon getting this final byte, trigger the speed enhancement
98 switch and go to DONE.
99
100 DONE:
101
102 Final state, nothing more happens.