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comparison doc/PPS-catcher-FSM @ 34:c2fc75655937

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doc/PPS-catcher-FSM: it has been implemented
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 22:58:26 +0000
parents f1e7795557b1
children 1068f9fd41d5
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33:28ffdfa193f3 34:c2fc75655937
1 This document describes the PPS catcher state machine (to be implemented in the 1 This document describes the PPS catcher state machine that has been implemented
2 sniffer FPGA) in verbal pseudocode. 2 in the SIMtrace3 sniffer FPGA, using a sort of verbal pseudocode.
3 3
4 INITIAL: 4 INITIAL:
5 5
6 This state will be entered upon reset (held in this state while RST is low). 6 This state will be entered upon reset (held in this state while RST is low).
7 Must receive 8'h3B to proceed to state T0, otherwise transition to DONE. 7 Must receive 8'h3B to proceed to state T0, otherwise transition to DONE.