FreeCalypso > hg > fc-sim-sniff

comparison fpga/sniffer-basic/Makefile @ 13:82da4b7835b7

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
FPGA Makefile: generate timing.rpt
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 01:12:16 +0000
parents d29dcfa78124
children af1a9732da1f
comparison
equal deleted inserted replaced
12:d29dcfa78124 13:82da4b7835b7
1 VSRC= clk_edge.v reset_detect.v sniff_rx.v sync_inputs.v top.v uart_tx.v 1 VSRC= clk_edge.v reset_detect.v sniff_rx.v sync_inputs.v top.v uart_tx.v
2 PCF= icestick.pcf 2 PCF= icestick.pcf
3 PROJ= fpga 3 PROJ= fpga
4 4
5 all: ${PROJ}.bin 5 all: ${PROJ}.bin timing.rpt
6 6
7 ${PROJ}.json: ${VSRC} 7 ${PROJ}.json: ${VSRC}
8 yosys-wrap top $@ ${VSRC} | tee synthesis.rpt 8 yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
9 9
10 ${PROJ}.asc: ${PROJ}.json ${PCF} 10 ${PROJ}.asc: ${PROJ}.json ${PCF}
12 --json ${PROJ}.json -l pnr.rpt 12 --json ${PROJ}.json -l pnr.rpt
13 13
14 ${PROJ}.bin: ${PROJ}.asc 14 ${PROJ}.bin: ${PROJ}.asc
15 icepack $< $@ 15 icepack $< $@
16 16
17 timing.rpt: ${PROJ}.asc
18 icetime -d hx1k -mtr $@ $<
19
17 clean: 20 clean:
18 rm -f *.json *.asc *.bin 21 rm -f *.json *.asc *.bin