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comparison fpga/sniffer-basic/top.v @ 6:7db5fd6646df

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fpga/sniffer-basic: initial version
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 00:52:00 +0000
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children 3da4676dafa8
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5:07c5aac6e84f 6:7db5fd6646df
1 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
2 UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST, SIM_CLK, SIM_IO);
3
4 input CLK12;
5 output LED1, LED2, LED3, LED4, LED5;
6
7 input UART_TxD, UART_RTS, UART_DTR;
8 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
9
10 input SIM_RST, SIM_CLK, SIM_IO;
11
12 /* input synchronizers */
13
14 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
15
16 sync_inputs sync (CLK12, SIM_RST, SIM_RST_sync, SIM_CLK, SIM_CLK_sync,
17 SIM_IO, SIM_IO_sync);
18
19 /* character receiver */
20
21 wire Rx_strobe, Rx_error;
22 wire [7:0] Rx_char;
23 wire Rx_start_bit, Rx_parity_bit;
24
25 sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
26 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
27
28 /* explicit detection of RST transitions */
29
30 wire SIM_RST_toggle;
31
32 reset_detect reset_detect (CLK12, SIM_RST_sync, SIM_RST_toggle);
33
34 /* output to the host */
35
36 wire Tx_trigger;
37 wire [15:0] Tx_data;
38
39 assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
40 assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,3'b000,
41 Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};
42
43 uart_tx uart_tx (CLK12, Tx_trigger, Tx_data, UART_RxD);
44
45 /* UART modem control outputs: unused */
46
47 assign UART_CTS = 1'b1;
48 assign UART_DSR = 1'b0;
49 assign UART_DCD = 1'b0;
50
51 /* board LEDs */
52
53 assign LED1 = 1'b1;
54 assign LED2 = 1'b0;
55 assign LED3 = 1'b1;
56 assign LED4 = 1'b0;
57 assign LED5 = !SIM_RST;
58
59 endmodule