FreeCalypso > hg > fc-sim-sniff

comparison fpga/sniffer-pps/sync_inputs.v @ 28:0f74428c177c

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
fpga/sniffer-pps: first version
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 20:05:23 +0000
parents fpga/sniffer-basic/sync_inputs.v@7db5fd6646df
children
comparison
equal deleted inserted replaced
27:990ecafdddb4 28:0f74428c177c
1 /*
2 * This Verilog module captures the input synchronizer logic: passing all 3
3 * SIM sniffer inputs through double-DFF synchronizers to bring them into
4 * our internal clock domain.
5 */
6
7 module sync_inputs (IntClk, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
8 SIM_IO_in, SIM_IO_sync);
9
10 input IntClk;
11 input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
12 output SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
13 reg SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
14
15 reg SIM_RST_sync1, SIM_CLK_sync1, SIM_IO_sync1;
16
17 always @(posedge IntClk)
18 SIM_RST_sync1 <= SIM_RST_in;
19
20 always @(posedge IntClk)
21 SIM_RST_sync <= SIM_RST_sync1;
22
23 always @(posedge IntClk)
24 SIM_CLK_sync1 <= SIM_CLK_in;
25
26 always @(posedge IntClk)
27 SIM_CLK_sync <= SIM_CLK_sync1;
28
29 always @(posedge IntClk)
30 SIM_IO_sync1 <= SIM_IO_in;
31
32 always @(posedge IntClk)
33 SIM_IO_sync <= SIM_IO_sync1;
34
35 endmodule