FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/top.v @ 7:beeda5368a77

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.hgignore: add FPGA build products
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 00:54:09 +0000
parents 7db5fd6646df
children 3da4676dafa8
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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1 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
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2 UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST, SIM_CLK, SIM_IO);
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4 input CLK12;
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5 output LED1, LED2, LED3, LED4, LED5;
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7 input UART_TxD, UART_RTS, UART_DTR;
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8 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
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10 input SIM_RST, SIM_CLK, SIM_IO;
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12 /* input synchronizers */
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14 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
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16 sync_inputs sync (CLK12, SIM_RST, SIM_RST_sync, SIM_CLK, SIM_CLK_sync,
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17 SIM_IO, SIM_IO_sync);
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19 /* character receiver */
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21 wire Rx_strobe, Rx_error;
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22 wire [7:0] Rx_char;
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23 wire Rx_start_bit, Rx_parity_bit;
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25 sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
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26 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
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28 /* explicit detection of RST transitions */
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30 wire SIM_RST_toggle;
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32 reset_detect reset_detect (CLK12, SIM_RST_sync, SIM_RST_toggle);
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34 /* output to the host */
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36 wire Tx_trigger;
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37 wire [15:0] Tx_data;
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39 assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
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40 assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,3'b000,
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41 Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};
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43 uart_tx uart_tx (CLK12, Tx_trigger, Tx_data, UART_RxD);
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45 /* UART modem control outputs: unused */
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46
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47 assign UART_CTS = 1'b1;
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48 assign UART_DSR = 1'b0;
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49 assign UART_DCD = 1'b0;
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51 /* board LEDs */
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53 assign LED1 = 1'b1;
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54 assign LED2 = 1'b0;
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55 assign LED3 = 1'b1;
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56 assign LED4 = 1'b0;
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57 assign LED5 = !SIM_RST;
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59 endmodule