FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/reset_detect.v @ 22:b112c2df6c43

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sw: simtrace3-sniff-rx program written, compiles
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 22 Aug 2023 06:16:44 +0000
parents 7db5fd6646df
children
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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1 /*
7db5fd6646df fpga/sniffer-basic: initial version
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2 * This Verilog module captures the logic that detects SIM_RST transitions
7db5fd6646df fpga/sniffer-basic: initial version
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3 * in either direction.
7db5fd6646df fpga/sniffer-basic: initial version
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4 */
7db5fd6646df fpga/sniffer-basic: initial version
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7db5fd6646df fpga/sniffer-basic: initial version
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6 module reset_detect (IntClk, SIM_RST_sync, SIM_RST_toggle);
7db5fd6646df fpga/sniffer-basic: initial version
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7
7db5fd6646df fpga/sniffer-basic: initial version
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8 input IntClk;
7db5fd6646df fpga/sniffer-basic: initial version
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9 input SIM_RST_sync;
7db5fd6646df fpga/sniffer-basic: initial version
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10 output SIM_RST_toggle;
7db5fd6646df fpga/sniffer-basic: initial version
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7db5fd6646df fpga/sniffer-basic: initial version
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12 reg prev_state;
7db5fd6646df fpga/sniffer-basic: initial version
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14 always @(posedge IntClk)
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15 prev_state <= SIM_RST_sync;
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7db5fd6646df fpga/sniffer-basic: initial version
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17 assign SIM_RST_toggle = SIM_RST_sync != prev_state;
7db5fd6646df fpga/sniffer-basic: initial version
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18
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19 endmodule