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annotate boards/mv-sniffer/src/Makefile @ 8:7cab8e0dd937

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FPGA Makefile: yosys-wrap installed on Mother's system
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Aug 2023 00:55:33 +0000
parents 0c321f1ce085
children
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1 BOMS= tallied-bom.txt tallied-bom.csv comptab.txt
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81f3c1eef065 boards/mv-sniffer/src: components bound to MCL
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2 NETS= sverp.unet bound.unet pcb-netlist.txt
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0c321f1ce085 boards/mv-sniffer/src: generate elements.pcb
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4 all: ${BOMS} ${NETS} elements.pcb
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6 sverp.unet: schem.v ic_74LVC4T3144.v primitives
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7 ueda-sverp -o $@ schem.v ic_74LVC4T3144.v
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9 bound.unet: MCL sverp.unet
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10 unet-bind -c sverp.unet $@
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12 pcb-netlist.txt: bound.unet
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13 unet2pcb bound.unet $@
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15 tallied-bom.txt: MCL
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16 ueda-mkbom -cr > $@
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18 tallied-bom.csv: MCL
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19 ueda-csvbom > $@
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21 comptab.txt: MCL
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22 ueda-shortbom > $@
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24 elements.pcb: MCL
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25 ueda-getfps -ch | ueda-runm4 > $@
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27 clean:
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28 rm -f *.unet *.txt *.csv errs elements.pcb