# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1590217426 0
# Node ID 4f40ae165be4072dedd93bb2bd5dffa08af74557
# Parent  4725fe5932c4cb0819fbcdbe2129029542fbedfa
abb.c & init.c: sync with Magnetite for Luna additions

These Luna target-specific additions are conditionalized on CONFIG_TARGET_LUNA,
a C preprocessor symbol that will never be defined in Selenite, hence this
change has exactly zero impact on FC Selenite.  However, they are being pulled
in as a sync in order to keep the diff between Magnetite and Selenite to a
minimum; keeping this diff to a minimum increases our opportunities for
possible evolution of future FC firmwares.

diff -r 4725fe5932c4 -r 4f40ae165be4 src/cs/drivers/drv_core/abb/abb.c
--- a/src/cs/drivers/drv_core/abb/abb.c	Fri May 22 18:04:44 2020 +0000
+++ b/src/cs/drivers/drv_core/abb/abb.c	Sat May 23 07:03:46 2020 +0000
@@ -92,6 +92,28 @@
 
 #define	ENABLE_BACKUP_BATTERY	0
 
+/*
+ * The following ABB_sleep_allowed global variable is yet another FreeCalypso
+ * addition.  Here is the issue: some handset boards have the controller/driver
+ * chip in the LCD powered from Iota VRIO, which is generally a very sensible
+ * arrangement.  As one reference example, our 176x220 pixel TFT LCDs which
+ * we are considering for our own FC handset draw about 3 mA from their Vci
+ * supply which we connect to VRIO - perfectly fine when the regulators are
+ * in their normal Active mode.  But what about sleep mode?  Sleep mode VRIO
+ * current limit is only 1 mA, thus the combination of the LCD being on and
+ * drawing 3 mA with the ABB in sleep mode is invalid.  TI's original code
+ * already had a check for VRPCSTS: PWON and RPWON need to be released and
+ * the charger needs to be unplugged in order to enter ABB superdeep sleep.
+ * We are extending this check with one more condition: ABB_sleep_allowed
+ * needs to be nonzero; the intent is that this variable will be set by the
+ * code responsible for putting the LCD into its own powerdown mode.
+ * This logic is included only for affected targets with LCDs.
+ */
+
+#ifdef CONFIG_TARGET_LUNA
+int ABB_sleep_allowed = 0;
+#endif
+
 #if (ABB_SEMAPHORE_PROTECTION)   
 
 static NU_SEMAPHORE abb_sem;
@@ -856,7 +878,11 @@
       // Read VRPCSTS register value and extract status of meaningfull inputs.  
       reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070;
 
+    #ifdef CONFIG_TARGET_LUNA
+      if (reg_val == 0x30 && ABB_sleep_allowed)
+    #else
       if (reg_val == 0x30)
+    #endif
       {
         // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit.
         ABB_WriteRegister(VRPCDEV, 0x02);  
diff -r 4725fe5932c4 -r 4f40ae165be4 src/cs/system/main/init.c
--- a/src/cs/system/main/init.c	Fri May 22 18:04:44 2020 +0000
+++ b/src/cs/system/main/init.c	Sat May 23 07:03:46 2020 +0000
@@ -557,6 +557,16 @@
         MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
         MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
+      #elif defined(CONFIG_TARGET_LUNA)
+        /*
+         * nCS0 is flash, nCS1 is XRAM, the LCD is connected to nCS3.
+         * nCS2 and nCS4 are currently unused.
+         */
+        MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(5, MEM_DVS_16, MEM_WRITE_EN, 1);
+        MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
       #elif (CHIPSET == 8)
         /*
          * Our only Calypso C05 target is Mother Mychaela's D-Sample board.