# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1532079481 0
# Node ID 4ab736fdbdba200a9e41f74187be7d4ce70b2a1a
# Parent  31384f415dae86bcd055697e4facda03319f04d3
targets/*.m4 created for linker script generation in gcc version

diff -r 31384f415dae -r 4ab736fdbdba targets/c11x.m4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/c11x.m4	Fri Jul 20 09:38:01 2018 +0000
@@ -0,0 +1,5 @@
+define(`FLASH_BOOT_VIA_BOOTROM',0)dnl
+define(`FLASHIMAGE_BASE_ADDR',0x10000)dnl
+define(`CONFIG_FWFLASH_SIZE',0x1C0000)dnl
+define(`CONFIG_IRAM_SIZE',0x40000)dnl
+define(`CONFIG_XRAM_SIZE',0x40000)dnl
diff -r 31384f415dae -r 4ab736fdbdba targets/c139.m4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/c139.m4	Fri Jul 20 09:38:01 2018 +0000
@@ -0,0 +1,5 @@
+define(`FLASH_BOOT_VIA_BOOTROM',0)dnl
+define(`FLASHIMAGE_BASE_ADDR',0x10000)dnl
+define(`CONFIG_FWFLASH_SIZE',0x3C0000)dnl
+define(`CONFIG_IRAM_SIZE',0x40000)dnl
+define(`CONFIG_XRAM_SIZE',0x80000)dnl
diff -r 31384f415dae -r 4ab736fdbdba targets/fcdev3b.m4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/fcdev3b.m4	Fri Jul 20 09:38:01 2018 +0000
@@ -0,0 +1,5 @@
+define(`FLASH_BOOT_VIA_BOOTROM',1)dnl
+define(`FLASHIMAGE_BASE_ADDR',0x2000)dnl
+define(`CONFIG_FWFLASH_SIZE',0x800000)dnl
+define(`CONFIG_IRAM_SIZE',0x80000)dnl
+define(`CONFIG_XRAM_SIZE',0x800000)dnl
diff -r 31384f415dae -r 4ab736fdbdba targets/gtamodem.m4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/gtamodem.m4	Fri Jul 20 09:38:01 2018 +0000
@@ -0,0 +1,5 @@
+define(`FLASH_BOOT_VIA_BOOTROM',1)dnl
+define(`FLASHIMAGE_BASE_ADDR',0x2000)dnl
+define(`CONFIG_FWFLASH_SIZE',0x300000)dnl
+define(`CONFIG_IRAM_SIZE',0x80000)dnl
+define(`CONFIG_XRAM_SIZE',0x100000)dnl
diff -r 31384f415dae -r 4ab736fdbdba targets/pirelli.m4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/pirelli.m4	Fri Jul 20 09:38:01 2018 +0000
@@ -0,0 +1,5 @@
+define(`FLASH_BOOT_VIA_BOOTROM',1)dnl
+define(`FLASHIMAGE_BASE_ADDR',0x2000)dnl
+define(`CONFIG_FWFLASH_SIZE',0x800000)dnl
+define(`CONFIG_IRAM_SIZE',0x80000)dnl
+define(`CONFIG_XRAM_SIZE',0x800000)dnl