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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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children c47e2dc10134
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-1:000000000000 0:b6a5e36de839
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_PWMGR.C
4 *
5 * Filename l1_pwmgr.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_PWMGR_C
11 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
12
13 #include "timer/timer2.h"
14 #include "armio/armio.h"
15
16 //omaps00090550 #include "l1_macro.h"
17 #include "l1_confg.h"
18
19 #if (OP_L1_STANDALONE == 1)
20 #include "uart/serialswitch_core.h"
21 #else
22 #include "uart/serialswitch.h"
23 #endif
24
25 #if (OP_L1_STANDALONE == 0)
26 #include "sim/sim.h"
27 #include "rv_swe.h"
28 #endif
29
30
31 #if (CODE_VERSION == SIMULATION)
32 #include "l1_types.h"
33 #include "l1_const.h"
34
35 #if (CHIPSET == 12) || (CHIPSET == 15)
36 #include "inth/sys_inth.h"
37 #include "sys_dma.h"
38 #include "ulpd.h"
39 #include "clkm.h"
40
41 // typedef volatile unsigned short REG_UWORD16; //omaps00090550
42 #define REG16(A) (*(REG_UWORD16*)(A))
43
44 #else
45 #include "inth/iq.h"
46 #endif
47
48 #if TESTMODE
49 #include "l1tm_defty.h"
50 #endif // TESTMODE
51
52 #if (AUDIO_TASK == 1)
53 #include "l1audio_const.h"
54 #include "l1audio_cust.h"
55 #include "l1audio_defty.h"
56 #endif // AUDIO_TASK
57
58 #if (L1_GTT == 1)
59 #include "l1gtt_const.h"
60 #include "l1gtt_defty.h"
61 #endif
62
63 #if (L1_MP3 == 1)
64 #include "l1mp3_defty.h"
65 #endif
66
67 #if (L1_MIDI == 1)
68 #include "l1midi_defty.h"
69 #endif
70 //ADDED FOR AAC
71 #if (L1_AAC == 1)
72 #include "l1aac_defty.h"
73 #endif
74 #include "l1_defty.h"
75 #include "l1_varex.h"
76 #include "l1_tabs.h"
77 #include "cust_os.h"
78 #include "l1_msgty.h"
79 #include "l1_proto.h"
80 #include "ulpd.h"
81 #include "l1_trace.h"
82
83 #if L1_GPRS
84 #include "l1p_cons.h"
85 #include "l1p_msgt.h"
86 #include "l1p_deft.h"
87 #include "l1p_vare.h"
88 #endif // L1_GPRS
89
90 #include <stdio.h>
91 #include "sim_cfg.h"
92 #include "sim_cons.h"
93 #include "sim_def.h"
94 #include "sim_var.h"
95 //omaps00090550
96 #include "nucleus.h"
97
98 extern NU_TASK L1S_task;
99 STATUS status;
100
101
102
103 #else // NO SIMULATION
104
105
106
107 #include "l1_types.h"
108 #include "l1_const.h"
109
110 #include "abb/abb.h"
111 #include "dma/sys_dma.h"
112
113 #if (OP_BT == 1)
114 #include "hci_ll_simul.h"
115 #endif
116
117 #if TESTMODE
118 #include "l1tm_defty.h"
119 #endif // TESTMODE
120
121 #if (AUDIO_TASK == 1)
122 #include "l1audio_const.h"
123 #include "l1audio_cust.h"
124 #include "l1audio_defty.h"
125 #endif // AUDIO_TASK
126
127 #if (L1_GTT == 1)
128 #include "l1gtt_const.h"
129 #include "l1gtt_defty.h"
130 #endif
131
132 #if (L1_MP3 == 1)
133 #include "l1mp3_defty.h"
134 #endif
135
136 #if (L1_MIDI == 1)
137 #include "l1midi_defty.h"
138 #endif
139 //ADDED FOR AAC
140 #if (L1_AAC == 1)
141 #include "l1aac_defty.h"
142 #endif
143 #include "l1_defty.h"
144 #include "l1_varex.h"
145 #include "l1_tabs.h"
146 #include "sys_types.h"
147 #include "tpudrv.h"
148 #include "cust_os.h"
149 #include "l1_msgty.h"
150 #include "l1_proto.h"
151 #include "l1_trace.h"
152 #include "timer/timer.h"
153
154 #if (CHIPSET == 12) || (CHIPSET == 15)
155 #include "timer/timer_sec.h"
156 #include "inth/sys_inth.h"
157
158 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */
159
160 #else //(CHIPSET == 12) || (CHIPSET == 15)
161 #include "inth/iq.h"
162 #include "inth/inth.h"
163 #endif
164 // #include "timer1.h"
165 #include "ulpd/ulpd.h"
166 #include "clkm/clkm.h"
167 #include "memif/mem.h"
168 #if L2_L3_SIMUL
169 #include "hw_debug.h"
170 #endif
171
172 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
173 #include "csmi/sleep.h"
174 #endif // OP_WCP
175 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
176 #include "sys_memif.h"
177 #endif
178
179 #if (GSM_IDLE_RAM != 0)
180 #if (OP_L1_STANDALONE == 1)
181 #include "csmi_simul.h"
182 #else
183 #include "csmi/csmi.h"
184 #endif
185 #endif
186
187 #if (CHIPSET == 15)
188 #include "drp_api.h"
189 #endif
190
191 #endif // NO SIMULATION
192
193 #if (CODE_VERSION != SIMULATION)
194 // for PTOOL compatibility
195 extern void INT_DisableIRQ(void);
196 extern void INT_EnableIRQ(void);
197 extern void l1dmacro_RF_sleep(void);
198 extern void l1dmacro_RF_wakeup(void);
199 WORD32 l1s_get_HWTimers_ticks(void);
200
201 // file timer1.h
202 SYS_UWORD16 Dtimer1_Get_cntlreg(void);
203 void Dtimer1_AR(unsigned short Ar);
204 void Dtimer1_PTV(unsigned short Ptv);
205 void Dtimer1_Clken(unsigned short En);
206 void Dtimer1_Start (unsigned short startStop);
207 void Dtimer1_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
208 SYS_UWORD16 Dtimer1_WriteValue (SYS_UWORD16 value);
209 SYS_UWORD16 Dtimer1_ReadValue (void);
210 #endif
211
212 void l1s_wakeup(void);
213 BOOL l1s_compute_wakeup_ticks(void);
214 void l1s_recover_Frame(void);
215 UWORD8 Cust_recover_Os(void);
216 void l1s_recover_HWTimers(void);
217 UWORD8 Cust_check_system(void);
218 void f_arm_sleep_cmd(UWORD8 d_sleep_mode);
219
220 //#if (TRACE_TYPE == 2) || (TRACE_TYPE == 3)
221 extern void L1_trace_string(char *s);
222 extern void L1_trace_char (char s);
223 //#endif
224 extern UWORD16 slp_debug_flag;
225
226 #if (GSM_IDLE_RAM != 0)
227 extern void l1s_trace_mftab(void);
228 #endif
229
230 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15)
231 extern T_DRP_REGS_STR *drp_regs;
232 #endif
233
234 #if L1_GPRS
235 WORD32 l1s_get_next_gauging_in_Packet_Idle(void);
236 #endif
237 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
238
239 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
240 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise
241
242 /************************************************************/
243 /* Macros for power management */
244 /************************************************************/
245 #define MIN(min, operand1) \
246 if (operand1 <= min) min = operand1;
247
248 // ex: RATIO T32khz/T4.33Mhz = 132.2428385417
249 // => root = integer part of the ratio
250 // = 132
251 // => frac = fractionnal part of the ratio multiplied by 65536 rounded to make it integer
252 // = 0.2428385417 * 65536 (Cf. ULPD specification)
253 // = 0.2428385417 * 2^16
254 // = 15914.66666689 = 15914
255
256 #define RATIO(HF,LF, root, frac) \
257 root = (UWORD32)(HF/LF); \
258 frac = (UWORD32)(((HF - (root*LF)) << 16) / LF);
259
260 // previous ratio with frac + 0.5
261 #if 0 /* original LoCosto code */
262 #define RATIO2(HF,LF, root, frac) \
263 if(LF){ \
264 root = (UWORD32)(HF/LF); \
265 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);}
266 #else /* FreeCalypso TCS211 reconstruction */
267 #define RATIO2(HF,LF, root, frac) \
268 { \
269 root = (UWORD32)(HF/LF); \
270 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);}
271 #endif
272
273 #define HFTHEO(LF, root, frac, hftheo) \
274 hftheo = root*LF + ((frac*LF) >>16);
275
276 #define SUM(HF, LF, nb, ind) \
277 LF=HF=0; \
278 for(ind=0; ind<nb; ind++) \
279 { \
280 LF = LF +l1s.pw_mgr.histo[ind][0]; \
281 HF = HF +l1s.pw_mgr.histo[ind][1]; \
282 }
283
284
285 #if 0 /* FreeCalypso TCS211 reconstruction */
286 T_PWMGR_DEBUG l1_pwmgr_debug;
287 #endif
288
289
290 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */
291
292
293 // l1ctl_pgm_clk32()
294 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN.
295
296 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz)
297 {
298 #if (CODE_VERSION != SIMULATION)
299 if (l1_config.pwr_mngt == PWR_MNGT)
300 {
301 UWORD32 inc_sixteen= 0, inc_frac=0, lf;
302
303 // REM: nb_hf is the real value of the high frequency (ex in nbr of 65Mhz clock)
304 // To compute the ratio, nb_hf must be expressed in nbr of clock 4.33 Mhz
305 // that's why nb_hf is divided by 3*l1_config.dpll
306 // RATIO2(nb_hf/(3*l1_config.dpll),nb_32khz,inc_sixteen,inc_frac);
307 // this line above is equal to the ligne below:
308 lf=(UWORD32)(3*l1_config.dpll*nb_32khz);
309 RATIO2(nb_hf,lf,inc_sixteen,inc_frac);
310
311 // integer part
312 ULDP_INCSIXTEEN_UPDATE(inc_sixteen);
313
314 // fractional part
315 ULDP_INCFRAC_UPDATE(inc_frac);
316 }
317 #endif
318 }
319
320
321 // l1ctl_gauging()
322 // Description: management of the gauging results
323 // At RESET state reset histogram and then go to INIT.
324 // At INIT state, go back to RESET on each */
325 // gauging > +- 100 ppm. If NB_INIT good gauging go to ACQUIS state.
326 // At ACQUIS state, go back to RESET on each gauging > (+- 20ppm +- 1us). If NB_ACQU good gauging */
327 // go to UPDATE state. Allow deep sleep feature.
328 // At UPDATE state, count consecutive gauging >+- 1 us.
329 // If MAX_BAD_GAUGING results go back to RESET.
330 // Otherwise re-enable deep sleep feature and reset bad results counter.
331
332 void l1ctl_gauging ( UWORD32 nb_32khz, UWORD32 nb_hf)
333 {
334 if (l1_config.pwr_mngt == PWR_MNGT)
335 {
336 enum states
337 {
338 RESET = 0,
339 INIT = 1,
340 ACQUIS = 2,
341 UPDATE = 3
342 };
343
344 static UWORD8 bad_count; // bad gauging values
345 static UWORD8 gauging_state= RESET; // RESET,INIT, ACQUIS, UPDATE
346 static UWORD8 nb_gaug; // number of gauging in ACQUIS
347 static UWORD8 idx,i; // index
348 static UWORD32 root, frac; // ratio of HF and LF average
349 UWORD32 sumLF, sumHF; // sum of HF and LF counts
350 double nbHF_theo;
351
352
353 // AFC or TEMPERATURE variation
354
355 //if ( (ABS( (WORD32)(l1s.pw_mgr.previous_afc-l1s.afc) ) > AFC_VARIATION) ||
356 // (ABS( (WORD32)(l1s.pw_mgr.previous_temp-l1s.afc) > TEMP_VARIATION) )
357 // gauging_state = RESET;
358
359 // reset state machine if not in IDLE mode
360 #if L1_GPRS
361 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) && (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED))
362 gauging_state = RESET;
363 #else
364 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) )
365 gauging_state = RESET;
366
367 #endif
368
369 switch (gauging_state)
370 {
371
372 case RESET:
373 {
374 UWORD8 i;
375
376 // Reset Histogram
377 for (i=0; i < SIZE_HIST; i++)
378 {
379 l1s.pw_mgr.histo[i][0] = 0;
380 l1s.pw_mgr.histo[i][1] = 0;
381 }
382 idx = 0;
383 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
384 gauging_state = INIT;
385 nb_gaug = NB_INIT; // counter for ACQUIS state
386 bad_count = 0; // reset count of BAD gauging
387
388 #if (TRACE_TYPE != 0)
389 l1_trace_gauging_reset();
390 #endif
391 }
392
393
394 case INIT:
395 {
396
397 // Acquire NB_INIT gauging wtw +- 100 ppm
398
399 if (l1a_l1s_com.mode != I_MODE) return;
400
401 // compute clocks ratio from measurements.
402 RATIO(nb_hf,nb_32khz,root,frac)
403
404
405 // allow [-500ppm,+100ppm] derive on 32Khz at startup.
406 #if 0 /* really old code, apparently */
407 if (
408 (root > l1s.pw_mgr.c_clk_min ||
409 (root == l1s.pw_mgr.c_clk_min &&
410 frac >= l1s.pw_mgr.c_clk_init_min) ) &&
411 (root < l1s.pw_mgr.c_clk_max ||
412 (root == l1s.pw_mgr.c_clk_max &&
413 frac <= l1s.pw_mgr.c_clk_init_max ) )
414 #elif 1 /* TCS211 reconstruction */
415 if (
416 (root == l1s.pw_mgr.c_clk_min &&
417 frac >= l1s.pw_mgr.c_clk_init_min ) ||
418 (root == l1s.pw_mgr.c_clk_max &&
419 frac <= l1s.pw_mgr.c_clk_init_max )
420 #else /* LoCosto code */
421 if (
422 ( l1s.pw_mgr.c_clk_min == l1s.pw_mgr.c_clk_max &&
423 frac >= l1s.pw_mgr.c_clk_init_min &&
424 frac <= l1s.pw_mgr.c_clk_init_max )
425 ||
426 ( l1s.pw_mgr.c_clk_min != l1s.pw_mgr.c_clk_max &&
427 ( (root == l1s.pw_mgr.c_clk_min &&
428 frac >= l1s.pw_mgr.c_clk_init_min ) ||
429 (root > l1s.pw_mgr.c_clk_min &&
430 root < l1s.pw_mgr.c_clk_max ) ||
431 (root == l1s.pw_mgr.c_clk_max &&
432 frac <= l1s.pw_mgr.c_clk_init_max ) ) )
433 #endif
434 )
435 {
436 l1s.pw_mgr.histo[idx ][0] = nb_32khz; // init histo with the number of 32kHz
437 l1s.pw_mgr.histo[idx++][1] = nb_hf; // init histo with the number of hf (13Mhz)
438
439 #if (CODE_VERSION == SIMULATION)
440 #if (TRACE_TYPE==5)
441 trace_ULPD("Gauging INIT Case ", l1s.actual_time.fn);
442 #endif
443 #endif
444
445 }
446 else
447 {
448 // out of the allowed derive -> reset
449 idx=0;
450 #if (TRACE_TYPE != 0)
451 l1_trace_gauging_reset();
452 #endif
453 }
454
455 if (idx == NB_INIT)
456 {
457 // enough measurement -> ACQUIS state
458 gauging_state = ACQUIS;
459 // compute clk ratio on count average
460 SUM(sumHF,sumLF, NB_INIT,i) // returns sumHF and sumLF
461 RATIO(sumHF,sumLF,root, frac) // returns root and frac*2E16, computed on the average
462 }
463 }
464 break;
465
466
467 case ACQUIS:
468 {
469 // Acquire NB_ACQU gauging at +-25ppm
470 // with jitter +- 1 us
471 UWORD8 n;
472
473 // from nb_32khz "measured"
474 // compute nbHF_theo
475 HFTHEO(nb_32khz,root,frac,nbHF_theo)
476
477 if ( (nb_hf >= (nbHF_theo - l1s.pw_mgr.c_delta_hf_acquis)) &&
478 (nb_hf <= (nbHF_theo + l1s.pw_mgr.c_delta_hf_acquis)) )
479 {
480 l1s.pw_mgr.histo[idx][0] = nb_32khz;
481 l1s.pw_mgr.histo[idx++][1] = nb_hf;
482 idx = idx % SIZE_HIST;
483
484 // compute clk ratio on count average
485 if(++nb_gaug >= SIZE_HIST) n=SIZE_HIST;
486 else n= nb_gaug;
487 SUM(sumHF,sumLF, n,i)
488 RATIO(sumHF,sumLF,root, frac)
489
490 #if (CODE_VERSION == SIMULATION)
491 #if (TRACE_TYPE==5)
492 trace_ULPD("Gauging ACQUIS Case ", l1s.actual_time.fn);
493 #endif
494 #endif
495
496 if ( nb_gaug == (NB_INIT+NB_ACQU)) // NB_ACQU good gauging
497 {
498 gauging_state = UPDATE; // UPDATE state
499 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
500 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
501 }
502 }
503 else
504 {
505 gauging_state = RESET;
506 }
507 }
508 break;
509
510 case UPDATE:
511 {
512
513 // Update gauging histogram
514 // compute nbHF theoric for ratio_avg
515 HFTHEO(nb_32khz,root,frac,nbHF_theo)
516
517 if ( (nb_hf >= (nbHF_theo-l1s.pw_mgr.c_delta_hf_update)) &&
518 (nb_hf <= (nbHF_theo+l1s.pw_mgr.c_delta_hf_update)) )
519 {
520 l1s.pw_mgr.histo[idx][0] = nb_32khz;
521 l1s.pw_mgr.histo[idx++][1] = nb_hf;
522
523 // compute clk ratio on count average
524 SUM(sumHF,sumLF, SIZE_HIST,i)
525 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
526
527 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
528 bad_count = 0; // reset count of BAD gauging
529
530 #if (CODE_VERSION == SIMULATION)
531 #if (TRACE_TYPE==5)
532 trace_ULPD("Gauging UPDATE Case ", l1s.actual_time.fn);
533 #endif
534 #endif
535
536 }
537 else
538 {
539 bad_count ++;
540 if (bad_count >= MAX_BAD_GAUGING) gauging_state = RESET;
541 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
542 }
543 idx = idx % SIZE_HIST;
544 }
545 break;
546 }
547 #if (TRACE_TYPE != 0) // Trace gauging
548 // save parameters in the corresponding structure
549 l1s.pw_mgr.state = gauging_state;
550 l1s.pw_mgr.lf = nb_32khz ;
551 // WARNING WARNING, this case gauging_state == UPDATE modify the algo.
552 // In case of trace the parameter root and frac are refresh.
553 // it is not the case if no trace and it seems there is mistake
554 #if 0 /* FreeCalypso TCS211 reconstruction */
555 if (gauging_state == UPDATE)
556 {
557 RATIO2(sumHF,sumLF,root,frac);
558 }
559 #endif
560 //End of Warning.
561 l1s.pw_mgr.hf = nb_hf ;
562 l1s.pw_mgr.root = root ;
563 l1s.pw_mgr.frac = frac ;
564 #endif // End Trace gauging
565 }
566 }
567
568
569 /* GAUGING_Handler() */
570 /* Description: update increment counter for 32Khz */
571 /* This interrupt function computes the ratio between */
572 /* HF/32Khz gauging counters and program ULPD increment */
573 /* values. */
574
575 void GAUGING_Handler(void)
576 {
577 #if (CODE_VERSION != SIMULATION)
578 if (l1_config.pwr_mngt == PWR_MNGT)
579 {
580 UWORD32 nb_32khz, nb_hf;
581
582 // Gauging task is ended
583 l1s.pw_mgr.gauging_task = INACTIVE;
584 #if (CHIPSET == 12) || (CHIPSET == 15)
585 F_INTH_DISABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT); // Mask ULPD GAUGING int.
586 #else
587 INTH_DISABLEONEIT(IQ_ULPD_GAUGING); // Mask ULPD GAUGING int.
588 #endif
589
590 // Number of 32 Khz clock at the end of the gauging
591 nb_32khz = ((*( UWORD16 *)ULDP_COUNTER_32_MSB_REG) * 65536) +
592 (*( UWORD16 *)ULDP_COUNTER_32_LSB_REG);
593
594 // Number of high frequency clock at the end of the gauging
595 // Convert it in nbr of 13 Mhz clocks (5*13=65Mhz)
596 nb_hf = ( ((*( UWORD16 *)ULDP_COUNTER_HI_FREQ_MSB_REG) * 65536) +
597 (*( UWORD16 *)ULDP_COUNTER_HI_FREQ_LSB_REG) ); // Divide by PLL ratio
598
599 l1ctl_gauging(nb_32khz, nb_hf);
600 }
601 #else //Simulation part
602
603 // Gauging task is ended
604 l1s.pw_mgr.gauging_task = INACTIVE;
605
606 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE);
607 #endif
608 }
609
610
611 // l1s_get_HWTimers_ticks()
612 // Description:
613 // evaluate the loading of the HW Timers for dep sleep
614 // BIG SLEEP: timers CLK may be stopped (user dependant)
615 // DEEP SLEEP:timers CLK and WTCHDOG CLK are stopped
616 // CLKS are enabled after VTCX0+SLICER+13MHZ
617 // setup time
618
619 WORD32 l1s_get_HWTimers_ticks(void)
620 {
621 #if (CODE_VERSION != SIMULATION)
622 WORD32 timer1,timer2,watchdog,HWTimer;
623 #if (CHIPSET == 12) || (CHIPSET == 15)
624 WORD32 watchdog_sec;
625 #endif
626 UWORD16 cntlreg;
627 UWORD16 modereg;
628 WORD32 old = 0;
629
630 // read Hercules Timers & Watchdog
631 //=================================================
632 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
633 // Tclk = 1.2308us for Fclk=13Mhz
634 // PTV = X (pre-scaler field)
635 //-------------------------------------------------
636 timer1 = timer2 = watchdog = HWTimer = -1;
637 #if (CHIPSET == 12) || (CHIPSET == 15)
638 watchdog_sec = -1;
639 #endif
640
641 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F
642 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
643 {
644 #if 0 /* match TCS211 object */
645 cntlreg = cntlreg&0x1F;
646 #endif
647 cntlreg >>= 2; // take PTV
648 cntlreg = 1 << (cntlreg+1);
649 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
650 if (timer1 <= MIN_SLEEP_TIME) return(0);
651 old = Dtimer1_ReadValue();
652 HWTimer = timer1;
653 }
654
655 cntlreg = Dtimer2_Get_cntlreg();
656 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
657 {
658 #if 0 /* match TCS211 object */
659 cntlreg = cntlreg&0x1F;
660 #endif
661 cntlreg >>= 2; // take PTV
662 cntlreg = 1 << (cntlreg+1);
663 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
664 if (timer2 <= MIN_SLEEP_TIME) return(0);
665 if (HWTimer == -1) HWTimer = timer2;
666 else MIN(HWTimer,timer2)
667 }
668
669 cntlreg = TIMER_Read(0); // AND 0x0f80
670 modereg = TIMER_Read(2);
671
672 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
673 {
674 // in watchdog mode PTV is forced to 7
675 if ( modereg & TIMER_WDOG )
676 cntlreg |= TIMER_PTV;
677
678 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
679 cntlreg = 1 << (cntlreg+1);
680 watchdog = (WORD32) ( ((TIMER_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
681 if (watchdog <= MIN_SLEEP_TIME) return(0);
682 if (HWTimer == -1) HWTimer = watchdog;
683 else MIN(HWTimer,watchdog)
684 }
685
686 #if (CHIPSET == 12) || (CHIPSET == 15)
687 /*
688 * Secure Watchdog Timer management
689 */
690 cntlreg = TIMER_SEC_Read(0); // AND 0x0f80
691 modereg = TIMER_SEC_Read(2);
692 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
693 {
694 // in watchdog mode PTV is forced to 7
695 if ( modereg & TIMER_WDOG )
696 cntlreg |= TIMER_PTV;
697
698 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
699 cntlreg = 1 << (cntlreg+1);
700 watchdog_sec = (WORD32) ( ((TIMER_SEC_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
701 if (watchdog_sec <= MIN_SLEEP_TIME) return(0);
702 if (HWTimer == -1) HWTimer = watchdog_sec;
703 else MIN(HWTimer,watchdog_sec)
704 }
705
706 #endif
707
708 return (HWTimer);
709 #else // simulation part
710 return (-1); // no HW timer in simulation
711 #endif
712 }
713
714 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled
715
716 void l1s_adapt_traffic_controller(void)
717 {
718 BOOL l1s_extram;
719 UWORD8 nb_bitmap;
720 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
721
722 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
723
724 l1s_extram = FALSE;
725
726 for(nb_bitmap=0; ((nb_bitmap < SIZE_TAB_L1S_MONITOR) && (l1s_extram == FALSE)); nb_bitmap++)
727 {
728 if (nb_bitmap == 1)
729 {
730 l1s_extram |= (((INT_RAM_GSM_IDLE_L1S_PROCESSES1 ^ gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) & gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) != 0);
731 }else
732 {
733 l1s_extram |= (gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap] != 0);
734 }
735 }
736
737 if ((l1s_extram != FALSE) && (!READ_TRAFFIC_CONT_STATE))
738 {
739 CSMI_TrafficControllerOn();
740 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
741 {
742 l1s_trace_mftab();
743 }
744 #endif
745 }
746 }
747 #endif
748
749 UWORD32 last_wakeup = 0;
750 UWORD8 wakeup_type; // Type of the interrupt
751 UWORD8 why_big_sleep; // Type of the big sleep
752
753 extern UWORD16 int_id;
754
755 // l1s_sleep_manager()
756 // Description:
757 // evaluate the loading of the system
758 // - SIM, UART, LCD ....
759 // - Nucleus tasks, Hisrs, timers
760 // - Timer1, Timer2, Watchdog
761 // program Big or Deep sleep
762
763 void l1s_sleep_manager()
764 {
765 //UWORD8 temp=0; OMAPS00090550
766
767 UWORD16 temp_clear_intr;
768
769 // fn when l1s_sleep_manager function is called
770 #if (CODE_VERSION != SIMULATION)
771 UWORD32 sleep_time = l1s.actual_time.fn_mod42432;
772 #else
773 UWORD32 sleep_time = l1s.actual_time.fn;
774 #endif
775
776 if (l1_config.pwr_mngt == PWR_MNGT)
777 {
778 // Power management is enabled
779 WORD32 min_time, HWtimer,wake_up_time,min_time_gauging;
780 WORD32 afc_fix;
781 static UWORD32 previous_sleep = CLOCK_STOP;
782 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
783 BOOL extended_page_mode_state = 0; //Store state of extended page mode
784 #endif
785 WORD32 time_from_last_wakeup=0;
786 UWORD32 sleep_mode;
787
788 #if (OP_BT == 1)
789 WORD32 hci_ll_status;
790 #endif
791
792 // init for trace and debug
793 why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED;
794 wakeup_type = WAKEUP_FOR_UNDEFINED;
795
796 time_from_last_wakeup = (sleep_time - last_wakeup + 42432) % 42432;
797
798 //=================================================
799 // check System (SIM, UART, LDC ..... )
800 //=================================================
801 sleep_mode = Cust_check_system();
802
803 if (sleep_mode == DO_NOT_SLEEP)
804 return;
805
806 #if (CODE_VERSION != SIMULATION)
807 //=================================================
808 // Protect System structures
809 // must be called BEFORE INT_DisableIRQ() while
810 // Nucleus does not restore IRQ/FIQ bits !!!!
811 //=================================================
812 OS_system_protect();
813 //=================================================
814 // Disable IRQ
815 //=================================================
816 INT_DisableIRQ();
817 #endif // NOT SIMULATION
818
819 //=================================================
820 // check OS loading
821 //=================================================
822 min_time = OS_get_inactivity_ticks();
823
824 //=================================================
825 // check HW Timers loading
826 //=================================================
827 HWtimer= l1s_get_HWTimers_ticks();
828
829 //=================================================
830 // check next gauging task for Packet Idle
831 //=================================================
832 #if L1_GPRS
833 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle();
834 #else
835 min_time_gauging = -1; // not used
836 #endif
837
838 #if (OP_BT == 1)
839 hci_ll_status = hci_ll_ok_for_sleep();
840 #endif
841 // check if immediate activity planned
842 // 0 means immediate activity
843 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM,
844 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames
845 // if MS can go in deep sleep
846 /*
847 * FreeCalypso change: the abstention from big sleep because of UART or SIM
848 * has been moved into Cust_check_system(), which now returns DO_NOT_SLEEP
849 * in these cases, while still returning FRAME_STOP if the cause is
850 * the backlight or charging.
851 */
852 if ( !min_time
853 || !HWtimer
854 || !min_time_gauging
855 #if 0 /* FreeCalypso change */
856 || (sleep_mode != CLOCK_STOP)
857 #endif
858 #if (OP_BT == 1)
859 || !hci_ll_status
860 #endif
861 )
862 {
863
864
865 #if (CODE_VERSION != SIMULATION)
866 OS_system_Unprotect();
867 // free System structure
868 // Enable all IRQ
869 INT_EnableIRQ();
870 // Wake up UART
871
872 SER_WakeUpUarts(); // Wake up Uarts
873
874 #endif
875 return;
876 }
877 //=================================================
878 // Select sleep duration ....
879 //=================================================
880 // remember: -1 means no activity planned
881 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31
882 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task,
883 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF
884
885 if (min_time == -1) min_time = l1a_l1s_com.time_to_next_l1s_task;
886 else MIN(min_time, l1a_l1s_com.time_to_next_l1s_task)
887 if (HWtimer != -1) MIN(min_time, HWtimer)
888 if (min_time_gauging != -1) MIN(min_time, min_time_gauging)
889
890 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
891 // to trace the Wake up source
892 // depending of min_time choose the wakeup_type
893 wakeup_type = WAKEUP_FOR_OS_TASK;
894 if (min_time == l1a_l1s_com.time_to_next_l1s_task) wakeup_type = WAKEUP_FOR_L1_TASK;
895 if (min_time == HWtimer) wakeup_type = WAKEUP_FOR_HW_TIMER_TASK;
896 if (min_time == min_time_gauging) wakeup_type = WAKEUP_FOR_GAUGING_TASK;
897 #endif
898
899 //=================================================
900 // Choose DEEP or BIG SLEEP
901 //=================================================
902 if ( ((l1s.pw_mgr.mode_authorized == DEEP_SLEEP) && (sleep_mode == CLOCK_STOP)) ||
903 ((l1s.pw_mgr.mode_authorized == ALL_SLEEP) && (sleep_mode == CLOCK_STOP)) )
904 {
905 // Check now gauging histogramme or if in inactive period of cell selection
906 #if (W_A_DSP_IDLE3 == 1) && (CODE_VERSION!=SIMULATION)
907 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
908 ( l1s_dsp_com.dsp_ndb_ptr->d_dsp_state == C_DSP_IDLE3))
909 #else
910 #if (CHIPSET == 12) || (CHIPSET == 15)
911 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
912 !CLKM_READ_nIDLE3)
913 #else
914 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0))
915 #endif
916 #endif
917 l1s.pw_mgr.sleep_performed = CLOCK_STOP;
918 else
919 {
920 // BIG SLEEP is chosen : check the reason
921 l1s.pw_mgr.sleep_performed = FRAME_STOP;
922 if (l1s.pw_mgr.enough_gaug != TRUE)
923 why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING;
924 else
925 why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES;
926 }
927 }
928 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP)
929 why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE;
930
931 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) ||
932 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) )
933 l1s.pw_mgr.sleep_performed = FRAME_STOP;
934
935
936 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7))
937 {
938 #if (CODE_VERSION != SIMULATION)
939 OS_system_Unprotect(); // free System structure
940 INT_EnableIRQ(); // Enable all IRQ
941
942 SER_WakeUpUarts(); // Wake up Uarts
943
944 #endif // NOT SIMULATION
945 return;
946 }
947
948 // update previous sleep
949 previous_sleep = l1s.pw_mgr.sleep_performed;
950
951
952 #if (CODE_VERSION != SIMULATION)
953
954 #if (CHIPSET == 12) || (CHIPSET == 15)
955 F_INTH_DISABLE_ONE_IT(C_INTH_FRAME_IT); // mask Frame int.
956 #else
957 INTH_DISABLEONEIT(IQ_FRAME); // mask Frame int.
958 #endif
959 #endif
960
961 //=====================================================
962 // if CLOCK_STOP : stop RF, TPU, asleep Omega, DPLL, SPI
963 // if FRAME_STOP : asleep Omega, SPI
964 //=====================================================
965 #if (CODE_VERSION != SIMULATION)
966 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
967 {
968 // ==== STop RF and TPU..... ===================
969
970 //L1_trace_string("Proceeding to Deep Sleep\n");
971
972
973 l1dmacro_RF_sleep();
974
975 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET |
976 // TSP_CTRL_RESET |TPU_CTRL_CLK_EN;
977 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =0;
978
979 //===== SET default value for gauging =========
980 // If we have come in here during the inactive period of cell
981 // selection, then load the ULPD timers with default values
982 // (used when the MS lost the network: in this case the deep sleep may be used)
983 if (l1a_l1s_com.mode == CS_MODE0)
984 {
985 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE, DEFAULT_32KHZ_VALUE);
986 }
987 }
988
989
990 //==============================================
991 // disable DPLL (do not provide clk to DSP & RIF (RIF))
992 //==============================================
993 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
994 // disable DPLL (do not provide clk to DSP & RIF (Bridge))
995 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS | CLKM_BRIDGE_DIS;
996 #endif
997
998 //==============================================
999 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
1000 //==============================================
1001 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc);
1002
1003 #if (OP_BT == 1)
1004 hci_ll_go_to_sleep();
1005 #endif
1006 //=================================================
1007 // STop SPI .....
1008 //=================================================
1009
1010 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
1011 #endif // NOT SIMULATION
1012
1013
1014 //=================================================
1015 // CQ19599: For Calypso+ chipset, extended page mode
1016 // shall be disabled before entering deep sleep and
1017 // restored at wake up
1018 //=================================================
1019 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
1020 extended_page_mode_state = (BOOL) f_memif_extended_page_mode_read_bit();
1021 f_memif_extended_page_mode_disable();
1022 #endif
1023
1024 //=================================================
1025 // Init the timer :
1026 //
1027 // a margin of 4 frames (>MIN_SLEEP_TIME) is taken
1028 // when evaluating system loading, because 1 frame
1029 // is lost for wakeup only, and because sleep
1030 // duration less than 1 frame is not worth ....
1031 //
1032 // 1 2 3 4 5 6 7 8
1033 // SLEEP_CTRL SLEEP WAKEUP TASK (RF,Timer, ...)
1034 //
1035 //=================================================
1036 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
1037 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1038 {
1039 // DEEP SLEEP -> need time to setup afc and rf
1040 wake_up_time = min_time - l1_config.params.setup_afc_and_rf;
1041 }
1042 else
1043 // BIG SLEEP
1044 wake_up_time = min_time - 1;
1045
1046
1047
1048 #if (CODE_VERSION != SIMULATION)
1049 if ( wake_up_time >= MAX_GSM_TIMER)
1050 ULDP_TIMER_INIT(MAX_GSM_TIMER);
1051 else
1052 ULDP_TIMER_INIT(wake_up_time);
1053
1054 ULDP_TIMER_LD; // Load the timer
1055
1056 // BUG3060. Clear pending IQ_TGSM from ULPD. This could happen in case ULPD was frozen
1057 // with zero into its GSM counter. In that case, the interrupt is still pending
1058 // and if it is not cleared, it wakes the board up just after switching the clock.
1059 // Clear it into the ULPD...
1060 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on
1061 //reading the register.
1062 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
1063 // ... and next into the INTH. (must be done in this order
1064
1065 #if (CHIPSET == 12) || (CHIPSET == 15)
1066 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
1067 F_INTH_ENABLE_ONE_IT(C_INTH_TGSM_IT);
1068 #else
1069 INTH_RESETONEIT(IQ_TGSM); // clear TDMA IRQ
1070 INTH_ENABLEONEIT(IQ_TGSM); // Unmask ULPD GSM int.
1071 #endif
1072
1073 #if (GSM_IDLE_RAM != 0)
1074 if (READ_TRAFFIC_CONT_STATE)
1075 {
1076 CSMI_TrafficControllerOff();
1077 }
1078 #endif
1079
1080 ULDP_TIMER_START; // start count down
1081
1082
1083 #if (GSM_IDLE_RAM_DEBUG == 1)
1084 (*( volatile unsigned short* )(0xFFFE4802)) &= ~ (1 << 2); // GPIO-2=0
1085 #endif
1086
1087 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1088 // DEEP SLEEP
1089 {
1090 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
1091 // specific sleep for WCP
1092 arm7_deep_sleep();
1093 #else // NO OP_WCP
1094 #if (W_A_CALYPSO_BUG_01435 == 1)
1095 f_arm_sleep_cmd(DEEP_SLEEP);
1096 #else
1097 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode
1098 #endif
1099 #endif // OP_WCP
1100 }
1101 else
1102 {
1103 // BIG SLEEP / l1s.pw_mgr.sleep_performed == FRAME_STOP
1104
1105 //==========================================================
1106 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized
1107 //==========================================================
1108
1109 UWORD16 clocks_stopped; //OMAPS90550- new
1110 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
1111 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
1112 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN);
1113 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
1114 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001);
1115
1116 #if (W_A_CALYPSO_BUG_01435 == 1)
1117 f_arm_sleep_cmd(BIG_SLEEP);
1118 #else
1119
1120 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // set big sleep mode
1121 #endif
1122 }
1123 #else // Simulation part
1124 l1s.pw_mgr.sleep_duration = wake_up_time;
1125 hw.deep_sleep_en = 1;
1126 status = NU_Suspend_Task(&L1S_task);
1127 // check status value...
1128 if (status)
1129 {
1130 #if (TRACE_TYPE==5)
1131 sprintf(errormsg,"Error somewhere in the L1S application to suspend : deep sleep\n");
1132 log_sim_error(ERR);
1133 #endif
1134 EXIT;
1135 }
1136 #endif // SIMULATION
1137
1138 //=================================================
1139 // Wake-up procedure
1140 //=================================================
1141 // Restore L1 data base, Nucleus, HW Timers ....
1142 //=================================================
1143
1144 #if (GSM_IDLE_RAM_DEBUG == 1)
1145 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1
1146 #endif
1147
1148
1149 l1s_wakeup();
1150
1151 last_wakeup = l1s.actual_time.fn_mod42432;
1152
1153 if (last_wakeup == sleep_time)
1154 // sleep duration == 0 -> wakeup in the same frame as sleep
1155 wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0;
1156
1157 #if (GSM_IDLE_RAM != 0)
1158 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending
1159 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration);
1160 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration);
1161
1162 if (l1s.pw_mgr.wakeup_type != WAKEUP_FOR_L1_TASK)
1163 {
1164 if (!READ_TRAFFIC_CONT_STATE)
1165 {
1166 CSMI_TrafficControllerOn();
1167 }
1168 }
1169 #endif
1170 //=================================================
1171 //if CLOCK_STOP : restart TPU and RF....
1172 //=================================================
1173 #if (CODE_VERSION != SIMULATION)
1174 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1175 {
1176 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN;
1177 UWORD8 local_sleep_status;
1178
1179 l1dmacro_RF_wakeup();
1180
1181 }
1182
1183 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
1184 // enable DPLL (provide clk to DSP & RIF(Bridge) in small/big sleep)
1185 // On CALYPSO, BRIDGE clock can be cut according to the ARM sleep mode even during DMA transfer
1186 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS | CLKM_BRIDGE_DIS);
1187 #elif (CHIPSET == 12)
1188 // Nothing to be done because if DSP wants clock, it will exit from IDLE3 mode, which wakes up the DPLL
1189 #elif (CHIPSET == 15)
1190 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
1191 #endif
1192
1193 //=================================================
1194 //if CLOCK_STOP or FRAME-STOP : ReStart SPI
1195 //=================================================
1196 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
1197
1198 //=================================================
1199 // Wake up ABB
1200 //=================================================
1201 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc);
1202
1203 #if (OP_BT == 1)
1204 hci_ll_wake_up();
1205 #endif
1206 #endif //CODE VERSION
1207
1208 //=================================================
1209 // CQ19599: For Calypso+ chipset, restore the extended
1210 // page mode if it was enabled before entering in sleep
1211 //=================================================
1212 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
1213 if ( extended_page_mode_state != 0 )
1214 f_memif_extended_page_mode_enable();
1215 #endif
1216
1217 #if (OP_L1_STANDALONE == 0)
1218 /*GC_Wakeup(); OMAPS00134004*/
1219 #endif
1220
1221 #if (CODE_VERSION != SIMULATION)
1222 //=================================================
1223 // enable IRQ
1224 //=================================================
1225 OS_system_Unprotect();
1226 #endif
1227
1228 #if (TRACE_TYPE != 0)
1229 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity
1230 {
1231 #if (GSM_IDLE_RAM == 0)
1232 l1_trace_sleep(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep);
1233 #else
1234 l1_trace_sleep_intram(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep);
1235 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
1236 l1s_trace_mftab();
1237 #endif
1238 #endif
1239 }
1240 #endif
1241
1242 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1243 trace_info.sleep_performed = TRUE;
1244 #endif
1245
1246 #if (CODE_VERSION != SIMULATION)
1247
1248 //=================================================
1249 // enable IRQ
1250 //=================================================
1251 INT_EnableIRQ();
1252
1253 //=================================================
1254 // Be careful:in case of asynchronous wake-up after sleep
1255 // an IT_TDMA may be unmasked and executed just after OS_system_Unprotect().
1256 // As we already are inside an hisr(), it implies the execution of an another hisr().
1257 // In order to avoid issues with the execution of an hisr() inside the hisr()
1258 // do not add code here after !!!
1259 // if possible respect this rule !
1260 //=================================================
1261
1262 //=================================================
1263 // wake-up UARTs
1264 //this function must be call after the UART interrupt,
1265 //it means after the function INT_EnableIRQ()
1266 //=================================================
1267 {
1268 #if (GSM_IDLE_RAM != 0)
1269 // Traffic controller has to be enabled before calling SER_WakeUpUarts
1270 // as this function can access the external RAM.
1271 // Reset the flag that will indicates if an interrup will put the traffic
1272 // controller ON during that time.
1273 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
1274 if (!READ_TRAFFIC_CONT_STATE)
1275 {
1276 flag_traffic_controller_state = 1;
1277 CSMI_TrafficControllerOn();
1278 }
1279 #endif
1280
1281
1282 SER_WakeUpUarts(); // Wake up Uarts
1283
1284
1285 #if (GSM_IDLE_RAM != 0)
1286 // The traffic controller state shall be restored as it was before
1287 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1288 // in between and activated the traffic controller.
1289 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
1290 {
1291 CSMI_TrafficControllerOff();
1292 }
1293 flag_traffic_controller_state = 0;
1294 #endif
1295 }
1296 #endif // NOT SIMULATION
1297 }
1298 }
1299
1300 // l1s_wakeup() */
1301 // Description: wake-up of the MCU from GSM Timer it OR unscheduled wake-up
1302 // This function read the TPU timer and fix the :
1303 // - system clock
1304 // - Nucleus timers
1305 // - L1 frame counter
1306 // - L1 next task counter
1307 // - Hardware timers
1308
1309 void l1s_wakeup(void)
1310 {
1311 #if (CODE_VERSION != SIMULATION)
1312 if (l1_config.pwr_mngt == PWR_MNGT)
1313 {
1314 // Restore interrupts ....
1315
1316 #if (CHIPSET == 12) || (CHIPSET == 15)
1317 // mask TGSM int.
1318 F_INTH_DISABLE_ONE_IT(C_INTH_TGSM_IT);
1319 #else
1320 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int.
1321 #endif
1322
1323 #if (CHIPSET == 12) || (CHIPSET == 15)
1324 int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
1325 if ( int_id >= 256 )
1326 int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100;
1327 #else
1328 int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
1329 if ( int_id >= 256 )
1330 int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100;
1331 #endif
1332
1333 // clear pending IQ_FRAME it and unmask it
1334 #if (CHIPSET == 12) || (CHIPSET == 15)
1335 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1336 F_INTH_ENABLE_ONE_IT(C_INTH_FRAME_IT); // Unmask FRAME int.
1337 #else
1338 INTH_RESETONEIT(IQ_FRAME); // clear TDMA IRQ
1339 INTH_ENABLEONEIT(IQ_FRAME); // Unmask FRAME int.
1340 #endif
1341
1342 #if (CHIPSET == 8)
1343 // if deep sleep
1344 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1345 {
1346 UWORD8 i;
1347
1348 // Loop with check whether DPLL is locked: 100 us max.
1349 for (i=0;i<16;i++)
1350 {
1351 if (DPLL_READ_DPLL_LOCK)
1352 break;
1353 }
1354 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
1355
1356 // Enable DPLL
1357 //--------------------------------------------------
1358 DPLL_SET_PLL_ENABLE;
1359
1360 // Loop with check whether DPLL is locked: 100 us max.
1361 for (i=0;i<16;i++)
1362 {
1363 if (DPLL_READ_DPLL_LOCK)
1364 break;
1365 }
1366 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
1367 } // if deep sleep
1368
1369 #endif // CHIPSET == 8
1370
1371 //=================================================
1372 //Restart PERIPHERALS clocks if necessary after a big sleep period
1373 // WARNING: restart other clocks modules!!!
1374 //=================================================
1375
1376
1377 #if(CHIPSET == 15)
1378 if(l1s.pw_mgr.sleep_performed == FRAME_STOP )
1379 {
1380
1381 //ABB_Wakeup_BS(); //Not Used
1382 //DBB_Wakeup_BS(); //Not Used
1383 }
1384 #else
1385 // if big sleep
1386 if ( l1s.pw_mgr.sleep_performed == FRAME_STOP )
1387 {
1388
1389 UWORD16 clocks_stopped;
1390 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
1391 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
1392 *((volatile UWORD16 *)ARMIO_CNTL_REG) |= ARMIO_CLOCKEN;
1393 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
1394 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) |= 0x0001;
1395
1396 }
1397 #endif
1398
1399
1400 /***************************************************/
1401 /* Compute effective sleeping time .... */
1402 /* */
1403 /* sleep duration is */
1404 /* - TIMER_INIT */
1405 /* - or TIMER_INIT - TIMER_VALUE */
1406 /* */
1407 /* "frame_adjust" = TRUE for unschedules wake-up */
1408 /* FALSE for scheduled wake-up */
1409 /***************************************************/
1410 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks();
1411
1412 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
1413 if ((l1s.pw_mgr.frame_adjust == TRUE))
1414 wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT;
1415 #endif
1416
1417
1418 /* Fix Frame */
1419
1420 l1s_recover_Frame();
1421
1422
1423 /* Fix Hardware Timers */
1424 /* */
1425 /* GSM 1.0 : ntd - timer clock not cut */
1426 /* */
1427 /* GSM 1.5 : deep sleep - need to fix timers */
1428
1429 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP)
1430 l1s_recover_HWTimers();
1431
1432
1433 /* Fix Os */
1434
1435 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
1436 }
1437 #else // SIMULATION part
1438 // update L1 timers (FN,...)
1439 l1s_recover_Frame();
1440 #endif
1441 }
1442
1443
1444
1445 /* l1s_wakeup_adjust() */
1446 /* Description: 1 frame adjust a fter unscheduled wake-up */
1447 /* This function fix the : */
1448 /* - system clock */
1449 /* - Nucleus timers */
1450 /* - L1 frame counter */
1451 /* - L1 next task counter */
1452 /* - Hardware timers */
1453
1454
1455 void l1s_wakeup_adjust ()
1456 {
1457 #if (CODE_VERSION != SIMULATION)
1458 if (l1_config.pwr_mngt == PWR_MNGT)
1459 {
1460
1461 UWORD32 previous_sleep_time;
1462
1463 /***************************************************/
1464 // Freeze GSM Timer .... */
1465 /***************************************************/
1466 ULDP_TIMER_FREEZE;
1467
1468 /***************************************************/
1469 // Compute effective sleeping time ....
1470 //
1471 // compute sleep duration
1472 // - TIMER_INIT
1473 // - or TIMER_INIT - TIMER_VALUE
1474 /***************************************************/
1475 // save sleep duration that was computed at "unscheduled wakeup"
1476 previous_sleep_time = l1s.pw_mgr.sleep_duration;
1477
1478 l1s_compute_wakeup_ticks();
1479
1480 // reset flag for adjustment request ....
1481 l1s.pw_mgr.frame_adjust = FALSE;
1482
1483 // fix sleep duration
1484 // => compute difference with duration computed at
1485 // "unscheduled wakeup"
1486 l1s.pw_mgr.sleep_duration -= previous_sleep_time;
1487
1488 // adjust system with 1 frame IF NECESSARY ....
1489 if (l1s.pw_mgr.sleep_duration)
1490 {
1491 /***************************************************/
1492 /* Fix Frame */
1493 /***************************************************/
1494 l1s_recover_Frame();
1495
1496 /***************************************************/
1497 /* Fix Os */
1498 /***************************************************/
1499 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
1500 }
1501 }
1502 #endif
1503 }
1504
1505
1506 /*-------------------------------------------------------*/
1507 /* l1s_compute_wakeup_Ticks() */
1508 /*-------------------------------------------------------*/
1509 /* */
1510 /* Description: wake-up */
1511 /* ------------ */
1512 /* This function compute the sleep duration according to */
1513 /* current value of count down counter. */
1514 /* - if TIMER_VALUE = 0 it returns TIMER_INIT */
1515 /* - else it returns TIMER_INIT-TIMER_VALUE*/
1516 /* */
1517 /*-------------------------------------------------------*/
1518 BOOL l1s_compute_wakeup_ticks(void)
1519 {
1520 UWORD16 temp_clear_intr;
1521 #if (CODE_VERSION != SIMULATION)
1522 // read current value of count down counter
1523 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_VALUE;
1524
1525 // if count down=0 it's a scheduled wake-up....
1526 if (l1s.pw_mgr.sleep_duration == 0)
1527 {
1528 // read sleeping planned value in TPU INIT register
1529 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT;
1530 // INTH is different from the ULPD interrupt -> aynchronous wakeup
1531 #if (CHIPSET == 12) || (CHIPSET == 15)
1532 if (int_id != C_INTH_TGSM_IT)
1533 #else
1534 if (int_id != IQ_TGSM)
1535 #endif
1536 {
1537 wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0;
1538 // RESET IT_ULPD in ULPD module
1539 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register
1540 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
1541 #if (CHIPSET == 12) || (CHIPSET == 15)
1542 // RESET IQ_TGSM (IT_ULPD) in IT register
1543 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
1544 // RESET IQ_FRAME in IT register
1545 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1546 int_id = C_INTH_TGSM_IT;
1547 #else
1548 // RESET IQ_TGSM (IT_ULPD) in IT register
1549 INTH_RESETONEIT(IQ_TGSM);
1550 // RESET IQ_FRAME in IT register
1551 INTH_RESETONEIT(IQ_FRAME);
1552 int_id = IQ_TGSM;
1553 #endif
1554 return(FALSE);
1555 }
1556 else
1557 return(FALSE);
1558 }
1559 else // Unscheduled wakeup
1560 {
1561 // read sleeping planned value in TPU INIT register & compute time elapsed
1562 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT - l1s.pw_mgr.sleep_duration;
1563 return(TRUE);
1564 }
1565 #else
1566 return(FALSE);//omaps00090550
1567 #endif
1568 }
1569
1570 /*-------------------------------------------------------*/
1571 /* l1s_recover_Frame() */
1572 /*-------------------------------------------------------*/
1573 /* */
1574 /* Description: adjust layer1 data from sleep duration */
1575 /* ------------ */
1576 /*-------------------------------------------------------*/
1577 void l1s_recover_Frame(void)
1578 {
1579 if (l1_config.pwr_mngt == PWR_MNGT)
1580 {
1581 /***************************************************/
1582 /* Fix Frame counters . */
1583 /***************************************************/
1584 l1s.debug_time += l1s.pw_mgr.sleep_duration; // used for debug and by L3 scenario.
1585
1586 // Time...
1587 // Update "actual time".
1588 l1s_increment_time(&(l1s.actual_time), l1s.pw_mgr.sleep_duration);
1589
1590 // Update "next time".
1591 l1s.next_time = l1s.actual_time;
1592 l1s_increment_time(&(l1s.next_time), 1); // Next time is actual_time + 1
1593
1594 #if L1_GPRS
1595 // Update "next plus time".
1596 l1s.next_plus_time = l1s.next_time;
1597 l1s_increment_time(&(l1s.next_plus_time), 1); // Next_plus time is next_time + 1
1598 #endif
1599
1600 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1601 trace_fct(CST_L1S_ADJUST_TIME, (UWORD32)(-1));
1602 #endif
1603
1604 // Multiframe table...
1605 // Increment active frame % mftab size.
1606 l1s.afrm = (l1s.afrm + l1s.pw_mgr.sleep_duration) % MFTAB_SIZE;
1607
1608 // Control function counters...
1609 // Increment frame count from last AFC update.
1610 l1s.afc_frame_count+= l1s.pw_mgr.sleep_duration;
1611 // reset counter to mask SNR/TOA results for 2 fr.
1612 #if (TOA_ALGO == 2)
1613 l1s.toa_var.toa_snr_mask=0;
1614 #else
1615 l1s.toa_snr_mask=0;
1616 #endif
1617
1618 /***************************************************/
1619 /* Fix next L1S task counter */
1620 /***************************************************/
1621 // Decrement time to next L1S task.
1622 if((l1a_l1s_com.time_to_next_l1s_task > 0) &&
1623 (l1a_l1s_com.time_to_next_l1s_task < MAX_FN))
1624 l1a_l1s_com.time_to_next_l1s_task -= l1s.pw_mgr.sleep_duration;
1625 } // l1_config.pwr_mngt == PWR_MNGT
1626 }
1627
1628
1629 /*-------------------------------------------------------*/
1630 /* l1s_recover_HWTimers() */
1631 /*-------------------------------------------------------*/
1632 /* */
1633 /* Description: adjust hardware timers from sleep */
1634 /* ------------ duration */
1635 /* */
1636 /* Timers clocks are enabled after VTCX0+SLICER+13MHZ */
1637 /* setup times. So sleep duration is : */
1638 /* GSM TIMER - SETUP_FRAME + SETUP_SLICER + SETUP_VTCXO */
1639 /* + SETUP_CLK13 */
1640 /*-------------------------------------------------------*/
1641
1642 void l1s_recover_HWTimers(void)
1643 {
1644 #if (CODE_VERSION != SIMULATION)
1645
1646 #define SETUP_FRAME_IN_CLK32 (SETUP_FRAME*4.615*32.768)
1647 #if (CHIPSET == 15)
1648 #define DELTA_TIME (0)
1649 #else
1650 #define DELTA_TIME (SETUP_FRAME_IN_CLK32 -SETUP_SLICER - SETUP_VTCXO)
1651 #endif
1652
1653
1654 if (l1_config.pwr_mngt == PWR_MNGT)
1655 {
1656 WORD32 timer1,timer2,timer;
1657 #if (CHIPSET == 12) || (CHIPSET == 15)
1658 WORD32 timer_sec;
1659 #endif
1660 UWORD16 cntlreg;
1661 UWORD16 modereg;
1662 double duration;
1663
1664
1665 //WORD32 old;- OMAPS 90550 new
1666
1667 // read Hercules Timers & Watchdog
1668 //=================================================
1669 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
1670 // Tclk = 1.2308us for Fclk=13Mhz
1671 // PTV = 7 (pre-scaler field)
1672 //-------------------------------------------------
1673
1674 cntlreg = Dtimer1_Get_cntlreg();
1675 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1676 {
1677 #if 0 /* match TCS211 object */
1678 cntlreg = cntlreg&0x1F;
1679 #endif
1680 cntlreg >>= 2; // take PTV
1681 cntlreg = 1 << (cntlreg+1); // compute 2^(PTV+1)
1682 // convert sleep duration in HWTimers ticks....
1683 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
1684 #if 0 /* match TCS211 object */
1685 if (duration < 0.0){
1686 duration = 0.0; // This needs to be done for all the timers
1687 }
1688 #endif
1689 timer1 = Dtimer1_ReadValue() - (UWORD16) duration;
1690
1691 Dtimer1_Start(0);
1692 Dtimer1_WriteValue(timer1);
1693 Dtimer1_Start(1);
1694 }
1695
1696 cntlreg = Dtimer2_Get_cntlreg();
1697 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1698 {
1699 #if 0 /* match TCS211 object */
1700 cntlreg = cntlreg&0x1F;
1701 #endif
1702 cntlreg >>= 2; // take PTV
1703 cntlreg = 1 << (cntlreg+1);
1704 // convert sleep duration in HWTimers ticks....
1705 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
1706 #if 0 /* match TCS211 object */
1707 if (duration < 0.0){
1708 duration = 0.0; // This needs to be done for all the timers
1709 }
1710 #endif
1711 timer2 = Dtimer2_ReadValue() - (UWORD16) duration;
1712 Dtimer2_Start(0);
1713 Dtimer2_WriteValue(timer2);
1714 Dtimer2_Start(1);
1715 }
1716
1717 cntlreg = TIMER_Read(0);
1718 modereg = TIMER_Read(2);
1719 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1720 {
1721 // in watchdog mode PTV is forced to 7
1722 if ( modereg & TIMER_WDOG )
1723 cntlreg |= TIMER_PTV;
1724
1725 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1726 cntlreg = 1 << (cntlreg+1);
1727 // convert sleep duration in HWTimers ticks....
1728 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
1729
1730 timer = TIMER_ReadValue() - (UWORD16) duration;
1731 TIMER_START_STOP(0);
1732 TIMER_WriteValue(timer);
1733 TIMER_START_STOP(1);
1734 }
1735
1736 #if (CHIPSET == 12) || (CHIPSET == 15)
1737 cntlreg = TIMER_SEC_Read(0);
1738 modereg = TIMER_SEC_Read(2);
1739 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1740 {
1741 // in watchdog mode PTV is forced to 7
1742 if ( modereg & TIMER_WDOG )
1743 cntlreg |= TIMER_PTV;
1744
1745 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1746 cntlreg = 1 << (cntlreg+1);
1747 // convert sleep duration in HWTimers ticks....
1748 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
1749
1750 timer_sec = TIMER_SEC_ReadValue() - (UWORD16) duration;
1751 TIMER_SEC_START_STOP(0);
1752 TIMER_SEC_WriteValue(timer_sec);
1753 TIMER_SEC_START_STOP(1);
1754 }
1755 #endif
1756
1757 }
1758 #endif
1759 }
1760 /*-------------------------------------------------------*/
1761 /* l1s_get_next_gauging_in_Packet_Idle() */
1762 /*-------------------------------------------------------*/
1763 /* */
1764 /* Description: */
1765 /* ------------ */
1766 /* return the nbr of frames before the next gauging */
1767 /* return -1 means no activity planned */
1768 /*-------------------------------------------------------*/
1769 #if L1_GPRS
1770 UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle
1771
1772 WORD32 l1s_get_next_gauging_in_Packet_Idle(void)
1773 {
1774 WORD32 next_gauging;
1775
1776 // gauging performed with Normal Paging (we are in Idle mode)
1777 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
1778 return (-1); // no activity planned
1779
1780 // we are not in Packet Idle Mode
1781 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED)
1782 return (-1); // no activity planned
1783
1784 next_gauging = next_gauging_scheduled_for_PNP - l1s.actual_time.fn ;
1785 if (next_gauging < 0)
1786 next_gauging+=MAX_FN;
1787
1788 if (next_gauging <= MIN_SLEEP_TIME)
1789 return(0);
1790
1791 return (next_gauging);
1792 }
1793 #endif
1794 /*-------------------------------------------------------*/
1795 /* l1s_gauging_decision_with_PNP() */
1796 /*-------------------------------------------------------*/
1797 /* */
1798 /* Description: */
1799 /* ------------ */
1800 /* */
1801 /*-------------------------------------------------------*/
1802 #if L1_GPRS
1803 BOOL l1s_gauging_decision_with_PNP(void)
1804 {
1805 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615)
1806
1807 /* reconstructed TCS211 code */
1808 if (l1s.actual_time.fn >= next_gauging_scheduled_for_PNP)
1809 {
1810 next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME;
1811 if (next_gauging_scheduled_for_PNP >= MAX_FN) next_gauging_scheduled_for_PNP -= MAX_FN;
1812 return (TRUE);
1813 }
1814
1815 return (FALSE); // do not perform gauging
1816 }
1817 #endif
1818 /*-------------------------------------------------------*/
1819 /* l1s_gauging_decision_with_NP() */
1820 /*-------------------------------------------------------*/
1821 /* */
1822 /* Description: */
1823 /* ------------ */
1824 /* */
1825 /*-------------------------------------------------------*/
1826 BOOL l1s_gauging_decision_with_NP(void)
1827 {
1828
1829 static UWORD8 time_to_gaug;
1830
1831 // a paging is scheduled or , was scheduled but discarded by a higher priority task
1832 if (l1s.pw_mgr.paging_scheduled == TRUE)
1833 {
1834 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag.
1835
1836 // A gauging session is needed : start gauging session with this paging bloc !
1837
1838 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
1839 // FreeCalypso TCS211 reconstruction: Nina's change reverted
1840 #if 1
1841 if (l1s.pw_mgr.enough_gaug != TRUE)
1842 time_to_gaug = 0;
1843 #else
1844 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1))
1845 {
1846 time_to_gaug = 0;
1847 l1s.force_gauging_next_paging_due_to_CCHR = 0;
1848 }
1849 #endif
1850 if (time_to_gaug > 0)
1851 {
1852 time_to_gaug--; // perform the gauging with an another paging.
1853 }
1854 else // perform the gauging with this paging
1855 {
1856 if (l1s.task_status[NP].current_status == ACTIVE )
1857 {
1858 time_to_gaug = GAUG_VS_PAGING_RATE[l1a_l1s_com.bs_pa_mfrms-2]-1;
1859
1860 return (TRUE); // gauging allowed
1861 }
1862 else // a gauging is scheduled to be perform here but the paging is missing
1863 { // (paging discarded by a higher priority task ?)
1864 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep until next gauging
1865 }
1866 }
1867 }
1868 return (FALSE); // gauging not allowed
1869 }
1870
1871 /*************************************************************/
1872 /* Gauging task management : */
1873 /* */
1874 /* CALYPSO */
1875 /* */
1876 /* 9 8 7 6 5 4 3 2 1 0 */
1877 /* C0 C1 C2 C3 C4 W R - - - */
1878 /* | | */
1879 /* | | */
1880 /* |_ start gauging |_ stop gauging */
1881 /* */
1882 /*OTHERS: */
1883 /* */
1884 /* 11 10 9 8 7 6 5 4 3 2 1 0 */
1885 /* C0 C1 C2 C3 C4 W R - - - - - */
1886 /* | | | | | */
1887 /* | | |_ start gauging |_ stop gauging */
1888 /* | | | | */
1889 /* | |_ (ITCOM) | |(ITCOM) */
1890 /* | | */
1891 /* |_ pgm PLL |_restore PLL */
1892 /* */
1893 /* */
1894 /*************************************************************/
1895 void l1s_gauging_task(void)
1896 {
1897 if (l1_config.pwr_mngt == PWR_MNGT)
1898 {
1899 /*************************************************************/
1900 if (l1s.pw_mgr.gauging_task == ACTIVE)
1901 {
1902 /*************************************************************/
1903 // COUNT = 10 ==> PLL is at 65 Mhz, start the gauging
1904 /*************************************************************/
1905 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
1906 // the gauging was started with the begining of the paging
1907 #else
1908 if (l1s.pw_mgr.gaug_count == (l1s.pw_mgr.gaug_duration-1))
1909 {
1910 #if (CODE_VERSION != SIMULATION)
1911 ULDP_GAUGING_START; // start gauging
1912 #endif
1913
1914 #if (TRACE_TYPE != 0)
1915 #if (GSM_IDLE_RAM != 0)
1916 l1_trace_gauging_intram();
1917 #else
1918 l1_trace_gauging();
1919 #endif
1920 #endif
1921 }
1922 #endif
1923
1924 l1s.pw_mgr.gaug_count--; // decrement counter
1925
1926
1927 // When a MISC task is enabled L1S must be ran every frame
1928 // to be able to enable the frame interrupt for DSP
1929 l1a_l1s_com.time_to_next_l1s_task = 0;
1930 }
1931
1932 /*************************************************************/
1933 // REQUEST A GAUGING PROCESS ON EACH PAGING BLOCK
1934 // IN IDLE MODE .....
1935 /*************************************************************/
1936
1937 else if (l1s.pw_mgr.gauging_task == INACTIVE )
1938 {
1939 BOOL decision = FALSE;
1940
1941 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
1942 decision = l1s_gauging_decision_with_NP();
1943 #if L1_GPRS
1944 else
1945 if (l1a_l1s_com.l1s_en_task[PNP] == TASK_ENABLED)
1946 decision = l1s_gauging_decision_with_PNP();
1947 #endif
1948
1949 if (decision == TRUE)
1950 {
1951 // gauging duration
1952 l1s.pw_mgr.gaug_count = l1s.pw_mgr.gaug_duration;
1953
1954 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
1955 // start ULPD gauging immediately with Calypso because we needn't IT_COM.
1956 #if (CODE_VERSION != SIMULATION)
1957 ULDP_GAUGING_START;
1958 #if (CHIPSET == 12) || (CHIPSET == 15)
1959 // Force the DPLL to be active
1960 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
1961 #endif
1962 #endif
1963
1964 #if (TRACE_TYPE != 0)
1965 #if (GSM_IDLE_RAM != 0)
1966 l1_trace_gauging_intram();
1967 #else
1968 l1_trace_gauging();
1969 #endif
1970 #endif
1971 #endif
1972
1973 // DSP programmation .......
1974 #if (DSP >= 33)
1975 #if (CHIPSET==4)
1976 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB;
1977 #endif
1978 #else
1979 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP
1980 #endif
1981
1982 l1s.pw_mgr.gauging_task = ACTIVE;
1983 }
1984 }
1985 }
1986 }
1987 /*-------------------------------------------------------*/
1988 /* l1s_gauging_task_end() */
1989 /*-------------------------------------------------------*/
1990 /* */
1991 /* Description: */
1992 /* ------------ */
1993 /* stop the gauging activity */
1994 /*-------------------------------------------------------*/
1995 void l1s_gauging_task_end(void)
1996 {
1997 if (l1_config.pwr_mngt == PWR_MNGT)
1998 {
1999 /*************************************************************/
2000 if (l1s.pw_mgr.gauging_task == ACTIVE)
2001 {
2002 /*************************************************************/
2003 // COUNT = 1 ==> stop the gauging and free DSP idle modes....
2004 /*************************************************************/
2005 if (l1s.pw_mgr.gaug_count == 1)
2006 {
2007 // wait for end of gauging interrupt ...
2008 l1s.pw_mgr.gauging_task = WAIT_IQ;
2009
2010 // Unmask ULPD GAUGING int.
2011 #if (CODE_VERSION != SIMULATION)
2012 #if (CHIPSET == 12) || (CHIPSET == 15)
2013 F_INTH_ENABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT);
2014 #else
2015 INTH_ENABLEONEIT(IQ_ULPD_GAUGING);
2016 #endif
2017 ULDP_GAUGING_STOP; // stop ULPD gauging
2018 #if (CHIPSET == 12) || (CHIPSET == 15)
2019 // Allow the DPLL to be cut according to ARM sleep mode
2020 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS);
2021 #endif
2022 #endif
2023
2024 // DSP programmation : free IDLE modes...
2025 #if (DSP >= 33)
2026 #if (CHIPSET==4)
2027 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB;
2028 #endif
2029 #else
2030 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1;
2031 #endif
2032
2033
2034 #if (CODE_VERSION == SIMULATION)
2035 // in order to simulate the Gauging interrupt
2036 GAUGING_Handler();
2037
2038 #if (TRACE_TYPE==5)
2039 trace_ULPD("Stop Gauging", l1s.actual_time.fn);
2040 #endif
2041 #endif
2042 }
2043 }
2044 }
2045 }
2046
2047 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
2048 #endif