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comparison src/cs/drivers/drv_core/inth/iq.h @ 0:b6a5e36de839

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src/cs: initial import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Jul 2018 04:39:26 +0000
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1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : iq.h
12
13 Description : Interrupt header
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.24
20
21 Date : 05/23/03
22
23 Previous delta : 12/19/00 14:22:53
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.iq.h
26
27 Sccs Id (SID) : '@(#) iq.h 1.13 01/30/01 10:22:22 '
28
29
30 *****************************************************************************/
31
32 #include "l1sw.cfg"
33 #include "board.cfg"
34 #include "chipset.cfg"
35 #include "swconfig.cfg"
36
37 #if (OP_L1_STANDALONE == 0)
38 #include "debug.cfg"
39 #endif
40
41 #if (OP_L1_STANDALONE == 0)
42 #include "main/sys_types.h"
43 #else
44 #include "sys_types.h"
45 #endif
46
47 // Hardware driver library build number
48 #define IQ_BUILD 1
49
50 #if (CHIPSET != 12)
51 #define WS_MASK 0x001F
52
53 #if (CHIPSET == 4)
54 #define IQ_NUM_INT 20
55 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
56 #define IQ_NUM_INT 25
57 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
58 #define IQ_NUM_INT 21
59 #else
60 #define IQ_NUM_INT 16
61 #endif
62
63
64 #define IRQ 0
65 #define FIQ 1
66
67 /*
68 * Interrupt bit numbers
69 */
70 #define IQ_WATCHDOG 0
71
72 #define IQ_TIM1 1
73 #define IQ_TIM2 2
74 #if (OP_L1_STANDALONE == 0)
75 #define IQ_TSP 3
76 #endif
77 #define IQ_FRAME 4
78 #define IQ_PAGE 5
79 #define IQ_SIM 6
80 #define IQ_UART_IT 7
81 #define IQ_ARMIO 8
82 #define IQ_RTC_TIMER 9
83 #define IQ_RTC_ALARM 10
84 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
85 #define IQ_TGSM 19
86 #else
87 #define IQ_TGSM 10
88 #endif
89 #define IQ_ULPD_GAUGING 11
90 #define IQ_EXT 12
91 #if (L1_DYN_DSP_DWNLD == 1)
92 #if ((CHIPSET == 10) || (CHIPSET == 11))
93 #define IQ_API 15
94 #endif // (CHIPSET == 10) || (CHIPSET == 11)
95 #endif // L1_DYN_DSP_DWNLD == 1
96
97
98 #if (OP_L1_STANDALONE == 0)
99 #define IQ_SIM_CD 16
100 #endif
101
102 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
103 #define IQ_UART_IRDA_IT 18
104 #endif
105
106 #if (OP_L1_STANDALONE == 0)
107 #define IQ_ICR 20
108 #endif
109
110 #if ((CHIPSET == 5) || (CHIPSET == 6))
111 #define IQ_GEA_IT 24
112 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
113 #define IQ_GEA_IT 20
114 #endif
115 #endif /* chipset != 12 */
116
117 /**** JTAG ID ****/
118 #define SATURN 0xB217
119 #define HERCRAM 0xB268
120 #define F731782 0xB2B5 // HERCROM OLD
121 #define F731782B 0xB2B5 // HERCROM 1M REV B
122 #define F731782A 0xB335 // HERCROM 1M REV A
123 #define F731950 0xB334 // HERCROM 2M
124 #if (CHIPSET == 4)
125 #define F731787 0xB2AC // HERCRAM20G
126 #endif
127 #if ((CHIPSET == 5) || (CHIPSET == 6))
128 #define F741709 0xB393 // HERCROM20G1
129 #endif
130 #if (CHIPSET == 9)
131 #define F751681 0xB217 // HERCROM200C035
132 #endif
133 #if (CHIPSET == 12)
134 #define F751997 0xB512 // HERCROM500G2C035
135 #endif
136
137
138 unsigned IQ_GetBuild(void);
139 #if (CHIPSET != 12)
140 void IQ_SetupInterrupts(void);
141 void IQ_Dummy(void);
142 #endif
143 void IQ_TimerHandler(void); /* Watchdog timer */
144 void IQ_TimerHandler1(void); /* timer 1 */
145 void IQ_TimerHandler2(void); /* timer 2 */
146 void IQ_FrameHandler(void); /* It Handler for TPU Frame IT NUCLEUS TICKS */
147 #if (CHIPSET != 12)
148 #if (OP_L1_STANDALONE == 0)
149 void IQ_IcrHandler32(void); // 32-bit ICR interrupt handler
150 #endif
151 void IQ_SetupInterruptEdge(unsigned short irq_num);
152 void IQ_SetupInterruptLevel(unsigned short irq_num);
153 void IQ_InitWaitState(unsigned short rom, unsigned short ram, unsigned short spy, unsigned short lcd, unsigned short jtag);
154 void IQ_Unmask(unsigned irqNum);
155 void IQ_Mask(unsigned irqNum);
156 void IQ_MaskAll(void);
157 #endif
158 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
159 void IQ_KeypadGPIOHandler (void);
160 #elif ((BOARD == 34) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45))
161 void IQ_KeypadHandler(void);
162 #endif
163 SYS_UWORD16 IQ_GetJtagId(void);
164 SYS_UWORD16 IQ_GetDeviceVersion(void);
165 SYS_BOOL IQ_RamBasedLead(void);
166 SYS_UWORD16 IQ_GetRevision(void);
167 void IQ_Gauging_Handler(void);
168 void IQ_External(void);
169 void IQ_Rtc_Handler(void);
170 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
171 void IQ_RtcA_Handler(void);
172 void IQ_GsmTim_Handler(void);
173 #if (L1_DYN_DSP_DWNLD == 1)
174 void IQ_ApiHandler(void);
175 #endif // L1_DYN_DSP_DWNLD
176 #else
177 void IQ_RtcA_GsmTim_Handler(void);
178 #endif
179 #if ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
180 // void IQ_GEA_Handler(void);
181 #endif
182
183 #if (OP_L1_STANDALONE == 0)
184 #if (TI_PROFILER == 1)
185 void IQ_InitLevel( SYS_UWORD16 inputInt,
186 SYS_UWORD16 FIQ_nIRQ,
187 SYS_UWORD16 priority,
188 SYS_UWORD16 edge );
189 #endif
190 #endif