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comparison src/cs/system/main/init.c @ 168:aa2956979fcb

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src/cs/system: MEMIF and init updates from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 19 Jun 2019 04:05:38 +0000
parents 7409b22cac61
children 4f40ae165be4
comparison
equal deleted inserted replaced
167:5b0e7f9b3d05 168:aa2956979fcb
360 * in their fw sets the ASIC_CONF register to 0x6050, 360 * in their fw sets the ASIC_CONF register to 0x6050,
361 * which means PWL on the LT/PWL pin and LPG on the 361 * which means PWL on the LT/PWL pin and LPG on the
362 * DSR_MODEM pin. 362 * DSR_MODEM pin.
363 */ 363 */
364 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050; 364 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050;
365 #elif defined(CONFIG_TARGET_GTAMODEM) 365 #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_GTM900)
366 /* 366 /*
367 * The DSR_MODEM/LPG Calypso signal is unconnected on 367 * The DSR_MODEM/LPG Calypso signal is unconnected on
368 * Openmoko's modem, so let's mux it as LPG (output) 368 * Openmoko's modem, so let's mux it as LPG (output)
369 * so it doesn't float, like Foxconn seem to have done 369 * so it doesn't float, like Foxconn seem to have done
370 * on the Pirelli. 370 * on the Pirelli.
371 *
372 * On the GTM900 module this signal is explicitly defined as LPG.
371 */ 373 */
372 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6040; 374 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6040;
373 #else 375 #else
374 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000; 376 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
375 #endif /* (BOARD == 35) */ 377 #endif /* (BOARD == 35) */
498 */ 500 */
499 RHEA_INITRHEA(0,0,0xFF); 501 RHEA_INITRHEA(0,0,0xFF);
500 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); 502 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
501 #if (CHIPSET == 8) 503 #if (CHIPSET == 8)
502 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6); 504 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6);
503 #elif (CHIPSET == 10) 505 #elif (CHIPSET == 10) || (CHIPSET == 11)
504 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); 506 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
505 #else 507 #else
506 #error "We only have DPLL setup for CHIPSETs 8 and 10" 508 #error "We only have DPLL setup for CHIPSETs 8 and 10"
507 #endif 509 #endif
508 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ 510 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
509 /* 511 /*
510 * FreeCalypso change: memory timings and widths 512 * FreeCalypso change: memory timings and widths are target-dependent;
511 * are target-dependent. 513 * please refer to the MEMIF-wait-states document in the freecalypso-docs
514 * repository for the full explanation.
512 */ 515 */
513 #ifdef CONFIG_TARGET_PIRELLI 516 #ifdef CONFIG_TARGET_PIRELLI
514 /* 517 /*
515 * Pirelli's version of this Init_Target() function 518 * Pirelli's version of this Init_Target() function
516 * in their fw does the following: 519 * in their fw does the following:
518 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); 521 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
519 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); 522 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
520 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); 523 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
521 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); 524 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
522 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0); 525 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
523 #elif defined(CONFIG_TARGET_FCFAM) 526 #elif defined(CONFIG_TARGET_C155)
524 /* 527 /*
525 * The settings currently adopted for the FreeCalypso 528 * C155/156 official fw MEMIF config is almost the same as Pirelli's,
526 * hardware family, only nCS0, nCS1 and nCS2 are used 529 * only nCS4 WS is different, but nCS4 is unused on this model...
527 * presently.
528 */ 530 */
529 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); 531 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
530 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); 532 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
531 MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0); 533 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
532 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); 534 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
533 MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0); 535 MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0);
534 #elif defined(CONFIG_TARGET_DSAMPLE) && (CHIPSET == 8) 536 #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
535 /* 537 defined(CONFIG_TARGET_GTAMODEM)
536 * On D-Sample C05 (older Calypso silicon version) the clocks
537 * run slower: the ARM clock runs at 39 MHz instead of 52 MHz.
538 * Therefore, we need to use fewer wait states to effect
539 * the same memory speed.
540 */
541 MEM_INIT_CS0(2, MEM_DVS_16, MEM_WRITE_EN, 0);
542 MEM_INIT_CS1(2, MEM_DVS_16, MEM_WRITE_EN, 0);
543 MEM_INIT_CS2(2, MEM_DVS_16, MEM_WRITE_EN, 0);
544 MEM_INIT_CS3(2, MEM_DVS_16, MEM_WRITE_EN, 0);
545 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
546 #else
547 /* 538 /*
548 * The original settings from Openmoko, 539 * The original settings from Openmoko,
549 * only nCS0 and nCS1 are actually used, 540 * only nCS0 and nCS1 are actually used,
550 * same as on Mot C1xx phones, 541 * same as on Mot C1xx phones,
551 * the nCS2/3/4 settings are dummies from TI. 542 * the nCS2/3/4 settings are dummies from TI.
553 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); 544 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
554 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); 545 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
555 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); 546 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
556 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); 547 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
557 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); 548 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
549 #elif defined(CONFIG_TARGET_J100)
550 /*
551 * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS:
552 * it appears that SE J100 has its ringtone melody generator chip
553 * hooked up there.
554 */
555 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
556 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
557 MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0);
558 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
559 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
560 #elif (CHIPSET == 8)
561 /*
562 * Our only Calypso C05 target is Mother Mychaela's D-Sample board.
563 * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns,
564 * so we should be good on this board.
565 */
566 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
567 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
568 MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0);
569 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
570 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
571 #elif (CHIPSET == 10) || (CHIPSET == 11)
572 /*
573 * Default for Calypso C035 targets in the absence of a more specific
574 * selection above. We put the WS=4 memory-oriented setting on all
575 * chip selects so we automatically cover targets with a second flash
576 * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even
577 * weirder targets with XRAM somewhere other than nCS1.
578 */
579 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
580 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
581 MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
582 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
583 MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
584 #else
585 #error "Unknown MEMIF configuration"
558 #endif 586 #endif
559 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0); 587 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
560 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0); 588 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
561 RHEA_INITAPI(0,1); 589 RHEA_INITAPI(0,1);
562 RHEA_INITARM(0,0); 590 RHEA_INITARM(0,0);