fc-selenite: src/cs/layer1/tpu_drivers/source0/tpudrv12.h annotate

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 112:fdecfb3bd860

.../drv_app/r2d/r2d_*.c: LCD include case fixes from Magnetite R2D is not used in Selenite, but we strive to keep the two source trees in sync as much as possible to reduce the diffs.

author	Mychaela Falconia <falcon@freecalypso.org>
date	Sat, 13 Oct 2018 16:56:22 +0000
parents	b6a5e36de839
children	df9c471ce9e9

rev	line source
0 b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /**************** Revision Controle System Header *********************
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * Copyright (c) Texas Instruments 1998
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Filename tpudrv12.h
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 **************** Revision Controle System Header *********************/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 //--- Configuration values
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 // TeST - Enable Main VCO buffer for test
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #include "rf.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "fc-target.cfg"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 //--- RITA PG declaration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 #define R_PG_10 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 #define R_PG_13 1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #define R_PG_20 2 // For RFPG 2.2, use 2.0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 #define R_PG_23 3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 //--- PA declaration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 #define PA_MGF9009 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 #define PA_RF3146 1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 #define PA_RF3133 2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #define PA_PF08123B 3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 #define PA_AWT6108 4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #if (RF_PA == PA_MGF9009 \|\| RF_PA == PA_PF08123B)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #define PA_CTRL_INT 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #define PA_CTRL_INT 1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 // This is also used in l1_rf12.h to select the SWAP_IQ
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #if (RF_PG >= R_PG_20)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around")
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #elif (RF_PG == R_PG_13)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 //- Bit definitions for TST register programings, etc
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #define BIT_0 0x000001
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #define BIT_1 0x000002
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 #define BIT_2 0x000004
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #define BIT_3 0x000008
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define BIT_4 0x000010
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #define BIT_5 0x000020
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #define BIT_6 0x000040
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #define BIT_7 0x000080
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #define BIT_8 0x000100
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #define BIT_9 0x000200
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #define BIT_10 0x000400
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #define BIT_11 0x000800
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 #define BIT_12 0x001000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #define BIT_13 0x002000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #define BIT_14 0x004000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 #define BIT_15 0x008000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #define BIT_16 0x010000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #define BIT_17 0x020000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #define BIT_18 0x040000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define BIT_19 0x080000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #define BIT_20 0x100000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 #define BIT_21 0x200000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 #define BIT_22 0x400000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #define BIT_23 0x800000
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 //--- TRF6151 definitions ------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 //- BASE REGISTER definitions
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #define REG_RX 0x000000 // MODE0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define REG_PLL 0x000001 // MODE1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 #define REG_PWR 0x000002 // MODE2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define REG_CFG 0x000003 // MODE3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 //- TeST REGISTER definitions => Used for WA only
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 // TeST - PLL2 WA => Define PLL2 TEST register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define TST_PLL2 0x00001E // MODE 14
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #define TST_VCO3 0x00000F // MODE 15 (016+151)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #define TST_VCO4 0x000024 // MODE 36 (216+41)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 // Alpha RF7 WA TeST registers
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #define TST_LDO 0x000027 // MODE 39 (216+71)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define TST_PLL1 0x00001D // MODE 29 (116+131)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 #define TST_TX2 0x000037 // MODE 55 (316+71)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 // More Alpha RF7 WA TeST registers
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 #define TST_TX3 0x00003C // MODE 61 (316+121)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #define TST_TX4 0x00003D // MODE 61 (316+131)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 // PG 2.1 WA TeST registers
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 #define TST_PLL3 0x00001F // MODE 31 (116+151)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 // #define TST_PLL4 0x00002C // MODE 44 (216+121)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #define TST_MISC 0x00003E // MODE 62 (316+141) => Used for setting the VCXO current
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 #define TST_LO 0x00001C // MODE 28 (116+121)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that,
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 // when accessed, triggers the copy of the serial registers.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 // This is necessary to switch into "manual operation mode"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 #define TX_LOOP_MANUAL BIT_3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 //- REG_RX - MODE0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define BLOCK_DETECT_0 BIT_3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 #define BLOCK_DETECT_1 BIT_4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #define RST_BLOCK_DETECT_0 BIT_5
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #define RST_BLOCK_DETECT_1 BIT_6
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 #define READ_EN BIT_7
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 #define RX_CAL_MODE BIT_8
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #define RF_GAIN (BIT_10 \| BIT_9)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 //- REG_PLL - MODE1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 //PLL_REGB
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 //PLL_REGA
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 //- REG_PWR - MODE2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #define BANDGAP_MODE_OFF 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #define BANDGAP_MODE_ON_ENA BIT_4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 #define BANDGAP_MODE_ON_DIS (BIT_4 \| BIT_3)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #define REGUL_MODE_ON BIT_5
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 // BIT[8..6] band
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 #define BAND_SELECT_GSM BIT_6
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 #define BAND_SELECT_DCS BIT_7
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 #define BAND_SELECT_850_LO BIT_8
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #define BAND_SELECT_850_HI (BIT_8 \| BIT_6)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 #define BAND_SELECT_PCS (BIT_8 \| BIT_7)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 #define SYNTHE_MODE_OFF 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 #define SYNTHE_MODE_RX BIT_9
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #define SYNTHE_MODE_TX BIT_10
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #define RX_MODE_OFF 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 #define RX_MODE_A BIT_11
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #define RX_MODE_B1 BIT_12
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #define RX_MODE_B2 (BIT_12 \| BIT_11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 #define TX_MODE_OFF 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 #define TX_MODE_ON BIT_13
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 #define PACTRL_APC_OFF 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define PACTRL_APC_ON BIT_14
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 #define PACTRL_APC_DIS 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #define PACTRL_APC_ENA BIT_15
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 //- REG_CFG - MODE3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 // Common PA controller settings:
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #define PACTRL_TYPE_PWR 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #define PACTRL_TYPE_CUR BIT_3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 #define PACTRL_IDIOD_30_UA 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define PACTRL_IDIOD_300_UA BIT_4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 // PA controller Clara-like (Power Sensing) settings:
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define PACTRL_VHOME_610_MV (BIT_7 \| BIT_5)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 #define PACTRL_VHOME_839_MV (BIT_7 \| BIT_5)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 #define PACTRL_VHOME_1000_MV (BIT_6 \| BIT_9)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 #define PACTRL_VHOME_1600_MV (BIT_8 \| BIT_5)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 #define PACTRL_RES_OPEN 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 #define PACTRL_RES_150_K BIT_10
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 #define PACTRL_RES_300_K BIT_11
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 #define PACTRL_RES_NU (BIT_10 \| BIT_11)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 #define PACTRL_CAP_0_PF 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 #define PACTRL_CAP_12_5_PF BIT_12
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 #define PACTRL_CAP_25_PF (BIT_13 \| BIT_12)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define PACTRL_CAP_50_PF BIT_13
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 // PACTRL_CFG contains the configuration of the PACTRL that will
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 // be put into the REG_CFG register at initialization time
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 // in this #define!!!
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 #if (RF_PA == 0) // MGF9009 (LCPA)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 #define PACTRL_CFG \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 PACTRL_IDIOD_300_UA \| \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 PACTRL_CAP_25_PF \| \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 PACTRL_VHOME_1000_MV \| \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 PACTRL_RES_300_K
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 #elif (RF_PA == 1) // 3146
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #define PACTRL_CFG 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 #elif (RF_PA == 2) // 3133
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 #define PACTRL_CFG 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 #elif (RF_PA == 3) // PF08123B
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define PACTRL_CFG \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 PACTRL_TYPE_PWR \| \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 PACTRL_CAP_50_PF \| \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 PACTRL_RES_300_K \| \
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 PACTRL_VHOME_610_MV
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #elif (RF_PA == 4) // AWT6108
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #define PACTRL_CFG 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #error Unknown PA specifiec!
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 // Temperature sensor
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #define TEMP_SENSOR_OFF 0x0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214 #define TEMP_SENSOR_ON BIT_14
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 // Internal Logic Init Disable
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 #define ILOGIC_INIT_DIS BIT_15
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 // It was introduced in PG 1.2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 // For previous PGs this BIT was unused, so it can be safelly programmed
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 // for all PGs
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 // RF signals connected to TSPACT [0..7]
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 #ifdef CONFIG_TARGET_PIRELLI
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 #define RF_RESET_LINE BIT_5
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 #define RF_RESET_LINE BIT_0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 #define RF_SER_ON RF_RESET_LINE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 #define RF_SER_OFF 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 #define TEST_TX_ON 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 #define TEST_RX_ON 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 #if defined(CONFIG_TARGET_LEONARDO) \|\| defined(CONFIG_TARGET_ESAMPLE)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 // 4-band config (E-sample, P2, Leonardo)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 #define FEM_7 BIT_2 // act2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 #define FEM_8 BIT_1 // act1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 #define FEM_9 BIT_4 // act4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 #define PA_HI_BAND BIT_3 // act3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 #define PA_LO_BAND 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 #define PA_OFF 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 #define FEM_OFF ( FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252 #define FEM_SLEEP ( 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 // This configuration is always inverted.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256 // RX_UP/DOWN and TX_UP/DOWN
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 #define RU_850 ( PA_OFF \| FEM_PINS ^ FEM_9 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277 #elif defined(CONFIG_TARGET_GTAMODEM) \|\| defined(CONFIG_TARGET_FCDEV3B)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 // Openmoko's triband configuration is a bastardized version
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 // of TI's quadband one from Leonardo/E-Sample
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282 #define FEM_7 BIT_2 // act2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 #define FEM_8 BIT_1 // act1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 #define FEM_9 BIT_4 // act4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 #define PA_HI_BAND BIT_3 // act3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 #define PA_LO_BAND 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 #define PA_OFF 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292 #define FEM_OFF ( FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 #define FEM_SLEEP ( 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296 // This configuration is always inverted.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298 // RX_UP/DOWN and TX_UP/DOWN
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 #define RU_1900 ( PA_OFF \| FEM_PINS ^ FEM_8 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319 #elif defined(CONFIG_TARGET_PIRELLI)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321 #define ANTSW_RX_PCS BIT_4
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 #define ANTSW_TX_HIGH BIT_10
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 #define ANTSW_TX_LOW BIT_11
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 #define PA_HI_BAND BIT_3 // act3
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 #define PA_LO_BAND 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327 #define PA_OFF 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 #define PA_ENABLE BIT_0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 // Pirelli uses a non-inverting buffer
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 #define FEM_OFF ( 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 #define FEM_SLEEP ( 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 // RX_UP/DOWN and TX_UP/DOWN (triband)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 #define RU_900 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 #define RD_900 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 #define TU_900 ( PA_LO_BAND \| ANTSW_TX_LOW )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 #define TD_900 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 #define RU_850 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 #define RD_850 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 #define TU_850 ( PA_LO_BAND \| ANTSW_TX_LOW )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 #define TD_850 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 #define RU_1800 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 #define RD_1800 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 #define TU_1800 ( PA_HI_BAND \| ANTSW_TX_HIGH )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 #define TD_1800 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 #define RU_1900 ( PA_OFF \| ANTSW_RX_PCS )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 #define RD_1900 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 #define TU_1900 ( PA_HI_BAND \| ANTSW_TX_HIGH )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #define TD_1900 ( PA_OFF \| 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 #elif defined(CONFIG_TARGET_COMPAL)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 #define PA_HI_BAND BIT_8 // act8
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 #define PA_LO_BAND 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 #define PA_OFF 0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 #define PA_ENABLE BIT_1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 // FEM control signals are active low
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 #define FEM_PINS (BIT_6 \| BIT_2)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 #define FEM_OFF ( FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 #define FEM_SLEEP ( 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 #define FEM_TX_HIGH BIT_6
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 #if USE_TSPACT2_FOR_TXLOW
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 #define FEM_TX_LOW BIT_2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 #define FEM_TX_LOW BIT_6
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 // RX_UP/DOWN and TX_UP/DOWN
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 #endif // FreeCalypso target selection
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 #ifdef CONFIG_TARGET_PIRELLI
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405 #define TC1_DEVICE_RF TC1_DEVICE1 // TSPEN1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 #else
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 //--- TIMINGS ----------------------------------------------------------
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 /------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 /* Download delay values */
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 /------------------------------------------/
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 #define T TPU_CLOCK_RANGE
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 // - TPU instruction into TSP timings ---
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 // 1 tpu instruction = 1 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 #define DLT_1 1 // 1 tpu instruction = 1 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 #define DLT_2 2 // 2 tpu instruction = 2 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 #define DLT_3 3 // 3 tpu instruction = 3 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 #define DLT_4 4 // 4 tpu instruction = 4 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 // - Serialization timings ---
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 // The following values where calculated with Katrin Matthes...
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed,
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed,
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 // ... while the following values are based on the HYP004.doc document
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed,
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 // i.e. 12 / 6 qbit = 2 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed,
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 // - TPU command execution + serialization length ---
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 #define DLT_1B 4 // 3*move + serialization of 7 bits
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 #define DLT_2B 7 // 4*move + serialization of 2 bytes
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 // - INIT (delta or DLT) timings ---
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 #define DLT_I2 8 // Time required to set RF_SER_OFF
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 #define DLT_I3 5 // Time required to set RF_SER_ON
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 #define DLT_I4 110 // Regulator Turn-ON time
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455 // - tdt & rdt ---
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 // MAX GSM (not GPRS) rdt and tdt values are...
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 //#define rdt 380 // MAX GSM rx delta timing
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 //#define tdt 400 // MAX GSM tx delta timing
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 // but current rdt and tdt values are...
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 #define rdt 0 // rx delta timing
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 #define tdt 0 // tx delta timing
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 // - RX timings ---
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 // - RX down:
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 // The times below are offsets to when BDLENA goes down
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469 // - RX up:
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 // The times below are offsets to when BDLENA goes high
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 // Burst data comes here
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 // - TX timings ---
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 // - TX down:
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 // The times below are offsets to when BULENA goes down
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 #if (PA_CTRL_INT == 1)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN.
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 #if (PA_CTRL_INT == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501 // - TX up:
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 // The times below are offsets to when BULENA goes high
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 //burst data comes here
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 #if (PA_CTRL_INT == 0)
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 #endif
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode"
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel
b6a5e36de839 src/cs: initial import from Magnetite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523

FreeCalypso > hg > fc-selenite

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 112:fdecfb3bd860